Patents by Inventor Satoshi Wakatsuki
Satoshi Wakatsuki has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230295801Abstract: According to one embodiment, a film forming method includes alternately performing a first process including at least two times of a first sequence and a second process including at least one time of a second sequence. The first sequence includes supplying a film forming gas into a film forming chamber, supplying a first purge gas into the film forming chamber, supplying a first reduction gas into the film forming chamber, and supplying a second purge gas into the film forming chamber, in order, and the second sequence includes supplying a second reduction gas into the film forming chamber, and supplying a third purge gas into the film forming chamber, in order.Type: ApplicationFiled: September 13, 2022Publication date: September 21, 2023Applicant: Kioxia CorporationInventors: Shigeru KINOSHITA, Hiroshi TOYODA, Satoshi WAKATSUKI, Masayuki KITAMURA, Naomi FUKUMAKI
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Patent number: 11705404Abstract: In one embodiment, a semiconductor device includes a substrate, and a plurality of insulating layers provided on the substrate. The device further includes a plurality of electrode layers provided on the substrate alternately with the plurality of insulating layers and including metal atoms and impurity atoms different from the metal atoms, lattice spacing between the metal atoms in the electrode layers being greater than lattice spacing between the metal atoms in an elemental substance of the metal atoms.Type: GrantFiled: April 15, 2021Date of Patent: July 18, 2023Assignee: Kioxia CorporationInventors: Satoshi Wakatsuki, Masayuki Kitamura, Atsuko Sakata
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Publication number: 20220195594Abstract: A semiconductor manufacturing apparatus includes a reaction chamber configured to perform a process on a semiconductor substrate using a gas mixture comprising a first gas, and a first path configured to exhaust resultant gas that comprises the first gas from the reaction chamber. The semiconductor manufacturing apparatus further includes a first trap provided in the first path and configured to extract at least a portion of the first gas from the resultant gas, and a second path in which the trap is not provided and configured to exhaust the resultant gas from the reaction chamber.Type: ApplicationFiled: March 9, 2022Publication date: June 23, 2022Applicant: KIOXIA CORPORATIONInventors: Masayuki KITAMURA, Atsuko SAKATA, Satoshi WAKATSUKI
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Patent number: 11355512Abstract: A semiconductor device includes a substrate, a logic circuit provided on the substrate, a wiring layer including a plurality of wirings that are provided above the logic circuit, a first insulating film below the wiring layer, a plug, and a second insulating film. Each of the wirings contains copper and extends along a surface plane of the substrate in a first direction. The wirings are arranged along the surface plane of the substrate in a second direction different from the first direction. The plug extends through the first insulating film in a third direction crossing the first and second directions and is electrically connected to one of the wirings. The plug contains tungsten. The second insulating film is provided between the first insulating film and the plug.Type: GrantFiled: February 25, 2020Date of Patent: June 7, 2022Assignee: KIOXIA CORPORATIONInventors: Jun Iijima, Masayoshi Tagami, Masayuki Kitamura, Satoshi Wakatsuki
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Patent number: 11322441Abstract: A semiconductor storage device according to an embodiment includes: an array chip having a memory cell array; a circuit chip having a circuit electrically connected to a memory cell; and a metal pad bonding the array chip and the circuit chip together. The metal pad includes an impurity. A concentration of the impurity is lowered as separating in a depth direction apart from a surface in a thickness direction of the metal pad.Type: GrantFiled: September 4, 2020Date of Patent: May 3, 2022Assignee: Kioxia CorporationInventor: Satoshi Wakatsuki
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Patent number: 11296109Abstract: A method of manufacturing a semiconductor device according to one embodiment includes forming a first film including a first metal above a processing target member. The method includes forming a second film including two or more types of element out of a second metal, carbon, and boron above the first film. The method includes forming a third film including the first metal above the second film. The method includes forming a mask film by providing an opening part to a stacked film including the first film, the second film and the third film. The method includes processing the processing target member by performing etching using the mask film as a mask.Type: GrantFiled: December 18, 2019Date of Patent: April 5, 2022Assignee: KIOXIA CORPORATIONInventors: Ryohei Kitao, Atsuko Sakata, Takeshi Ishizaki, Satoshi Wakatsuki, Shinichi Nakao, Shunsuke Ochiai, Kei Watanabe
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Publication number: 20220028739Abstract: A semiconductor device according to an embodiment includes: a barrier metal layer provided on a surface of an insulating layer; and a conductive layer having a first metal layer provided on a surface of the barrier metal layer, and a second metal layer provided on a surface of the first metal layer. The second metal layer includes an identical metal to metal of the first metal layer, and an impurity configured to remove fluorine bonded to the metal.Type: ApplicationFiled: October 6, 2021Publication date: January 27, 2022Applicant: Kioxia CorporationInventors: Satoshi WAKATSUKI, Tomohisa IINO, Naomi FUKUMAKI, Misuzu SATO, Masakatsu TAKEUCHI
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Patent number: 11139173Abstract: A production method of a semiconductor device includes introducing a reduction gas for reducing metal to a space containing a target to be used as the semiconductor device. The method also includes introducing a material gas and a first gas simultaneously to the space on a basis of a predetermined partial pressure ratio after introducing the reduction gas, to form a film that contains the metal, on the target. The material gas etches the metal when only the material gas is flowed. The first gas is different from the material gas. The predetermined partial pressure ratio is a ratio of the material gas and the first gas.Type: GrantFiled: July 10, 2018Date of Patent: October 5, 2021Assignee: TOSHIBA MEMORY CORPORATIONInventors: Katsuaki Natori, Satoshi Wakatsuki, Masayuki Kitamura
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Publication number: 20210296253Abstract: A semiconductor storage device according to an embodiment includes: an array chip having a memory cell array; a circuit chip having a circuit electrically connected to a memory cell; and a metal pad bonding the array chip and the circuit chip together. The metal pad includes an impurity. A concentration of the impurity is lowered as separating in a depth direction apart from a surface in a thickness direction of the metal pad.Type: ApplicationFiled: September 4, 2020Publication date: September 23, 2021Applicant: Kioxia CorporationInventor: Satoshi WAKATSUKI
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Patent number: 11127681Abstract: A semiconductor device includes a substrate. The semiconductor device further includes a wiring layer provided on the substrate, the wiring layer including a molybdenum layer including oxygen atoms as an impurity.Type: GrantFiled: February 19, 2019Date of Patent: September 21, 2021Assignee: TOSHIBA MEMORY CORPORATIONInventors: Satoshi Wakatsuki, Katsuaki Natori
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Publication number: 20210233872Abstract: In one embodiment, a semiconductor device includes a substrate, and a plurality of insulating layers provided on the substrate. The device further includes a plurality of electrode layers provided on the substrate alternately with the plurality of insulating layers and including metal atoms and impurity atoms different from the metal atoms, lattice spacing between the metal atoms in the electrode layers being greater than lattice spacing between the metal atoms in an elemental substance of the metal atoms.Type: ApplicationFiled: April 15, 2021Publication date: July 29, 2021Applicant: TOSHIBA MEMORY CORPORATIONInventors: Satoshi WAKATSUKI, Masayuki KITAMURA, Atsuko SAKATA
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Patent number: 11004804Abstract: In one embodiment, a semiconductor device includes a substrate, and a plurality of insulating layers provided on the substrate. The device further includes a plurality of electrode layers provided on the substrate alternately with the plurality of insulating layers and including metal atoms and impurity atoms different from the metal atoms, lattice spacing between the metal atoms in the electrode layers being greater than lattice spacing between the metal atoms in an elemental substance of the metal atoms.Type: GrantFiled: March 7, 2019Date of Patent: May 11, 2021Assignee: TOSHIBA MEMORY CORPORATIONInventors: Satoshi Wakatsuki, Masayuki Kitamura, Atsuko Sakata
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Patent number: 10978469Abstract: A semiconductor storage device includes a semiconductor substrate; an insulating layer provided on the semiconductor substrate; a barrier metal layer provided on the insulating layer; an aluminum compound layer provided on the barrier metal layer; an amorphous layer provided on the aluminum compound layer and including a material that vaporizes upon its chemical reaction with fluorine; and a metal layer provided on the amorphous layer.Type: GrantFiled: February 27, 2019Date of Patent: April 13, 2021Assignee: TOSHIBA MEMORY CORPORATIONInventors: Kensei Takahashi, Takashi Asano, Satoshi Wakatsuki
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Publication number: 20210082753Abstract: A semiconductor device according to an embodiment includes: a barrier metal layer provided on a surface of an insulating layer; and a conductive layer having a first metal layer provided on a surface of the barrier metal layer, and a second metal layer provided on a surface of the first metal layer. The second metal layer includes an identical metal to metal of the first metal layer, and an impurity configured to remove fluorine bonded to the metal.Type: ApplicationFiled: March 10, 2020Publication date: March 18, 2021Applicant: Kioxia CorporationInventors: Satoshi WAKATSUKI, Tomohisa IINO, Naomi FUKUMAKI, Misuzu SATO, Masakatsu TAKEUCHI
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Publication number: 20210082944Abstract: A semiconductor device includes a substrate, a logic circuit provided on the substrate, a wiring layer including a plurality of wirings that are provided above the logic circuit, a first insulating film below the wiring layer, a plug, and a second insulating film. Each of the wirings contains copper and extends along a surface plane of the substrate in a first direction. The wirings are arranged along the surface plane of the substrate in a second direction different from the first direction. The plug extends through the first insulating film in a third direction crossing the first and second directions and is electrically connected to one of the wirings. The plug contains tungsten. The second insulating film is provided between the first insulating film and the plug.Type: ApplicationFiled: February 25, 2020Publication date: March 18, 2021Inventors: Jun IIJIMA, Masayoshi TAGAMI, Masayuki KITAMURA, Satoshi WAKATSUKI
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Publication number: 20200127007Abstract: A method of manufacturing a semiconductor device according to one embodiment includes forming a first film including a first metal above a processing target member. The method includes forming a second film including two or more types of element out of a second metal, carbon, and boron above the first film. The method includes forming a third film including the first metal above the second film. The method includes forming a mask film by providing an opening part to a stacked film including the first film, the second film and the third film. The method includes processing the processing target member by performing etching using the mask film as a mask.Type: ApplicationFiled: December 18, 2019Publication date: April 23, 2020Applicant: TOSHIBA MEMORY CORPORATIONInventors: Ryohei KITAO, Atsuko SAKATA, Takeshi ISHIZAKI, Satoshi WAKATSUKI, Shinichi NAKAO, Shunsuke OCHIAI, Kei WATANABE
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Publication number: 20200091080Abstract: A semiconductor device includes a substrate. The semiconductor device further includes a wiring layer provided on the substrate, the wiring layer including a molybdenum layer including oxygen atoms as an impurity.Type: ApplicationFiled: February 19, 2019Publication date: March 19, 2020Applicant: Toshiba Memory CorporationInventors: Satoshi WAKATSUKI, Katsuaki NATORI
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Publication number: 20200091088Abstract: In one embodiment, a semiconductor device includes a substrate, and a plurality of insulating layers provided on the substrate. The device further includes a plurality of electrode layers provided on the substrate alternately with the plurality of insulating layers and including metal atoms and impurity atoms different from the metal atoms, lattice spacing between the metal atoms in the electrode layers being greater than lattice spacing between the metal atoms in an elemental substance of the metal atoms.Type: ApplicationFiled: March 7, 2019Publication date: March 19, 2020Applicant: TOSHIBA MEMORY CORPORATIONInventors: Satoshi WAKATSUKI, Masayuki KITAMURA, Atsuko SAKATA
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Publication number: 20200066750Abstract: A semiconductor storage device includes a semiconductor substrate; an insulating layer provided on the semiconductor substrate; a barrier metal layer provided on the insulating layer; an aluminum compound layer provided on the barrier metal layer; an amorphous layer provided on the aluminum compound layer and including a material that vaporizes upon its chemical reaction with fluorine; and a metal layer provided on the amorphous layer.Type: ApplicationFiled: February 27, 2019Publication date: February 27, 2020Applicant: TOSHIBA MEMORY CORPORATIONInventors: Kensei TAKAHASHI, Takashi ASANO, Satoshi WAKATSUKI
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Patent number: 10566280Abstract: In one embodiment, a semiconductor device includes a first insulator. The device further includes a metal layer that includes a first metal layer provided on a surface of the first insulator, and a second metal layer provided on a surface of the first metal layer and containing a first metallic element and oxygen or containing aluminum and nitrogen, or includes a third metal layer provided on the surface of the first insulator and containing a second metallic element, aluminum and nitrogen. The device further includes an interconnect material layer provided on a surface of the metal layer.Type: GrantFiled: August 14, 2018Date of Patent: February 18, 2020Assignee: TOSHIBA MEMORY CORPORATIONInventors: Satoshi Wakatsuki, Masayuki Kitamura, Takeshi Ishizaki, Hiroshi Itokawa, Daisuke Ikeno, Kei Watanabe, Atsuko Sakata