Patents by Inventor Satoshi Wakatsuki

Satoshi Wakatsuki has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11004804
    Abstract: In one embodiment, a semiconductor device includes a substrate, and a plurality of insulating layers provided on the substrate. The device further includes a plurality of electrode layers provided on the substrate alternately with the plurality of insulating layers and including metal atoms and impurity atoms different from the metal atoms, lattice spacing between the metal atoms in the electrode layers being greater than lattice spacing between the metal atoms in an elemental substance of the metal atoms.
    Type: Grant
    Filed: March 7, 2019
    Date of Patent: May 11, 2021
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Satoshi Wakatsuki, Masayuki Kitamura, Atsuko Sakata
  • Patent number: 10978469
    Abstract: A semiconductor storage device includes a semiconductor substrate; an insulating layer provided on the semiconductor substrate; a barrier metal layer provided on the insulating layer; an aluminum compound layer provided on the barrier metal layer; an amorphous layer provided on the aluminum compound layer and including a material that vaporizes upon its chemical reaction with fluorine; and a metal layer provided on the amorphous layer.
    Type: Grant
    Filed: February 27, 2019
    Date of Patent: April 13, 2021
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Kensei Takahashi, Takashi Asano, Satoshi Wakatsuki
  • Publication number: 20210082753
    Abstract: A semiconductor device according to an embodiment includes: a barrier metal layer provided on a surface of an insulating layer; and a conductive layer having a first metal layer provided on a surface of the barrier metal layer, and a second metal layer provided on a surface of the first metal layer. The second metal layer includes an identical metal to metal of the first metal layer, and an impurity configured to remove fluorine bonded to the metal.
    Type: Application
    Filed: March 10, 2020
    Publication date: March 18, 2021
    Applicant: Kioxia Corporation
    Inventors: Satoshi WAKATSUKI, Tomohisa IINO, Naomi FUKUMAKI, Misuzu SATO, Masakatsu TAKEUCHI
  • Publication number: 20210082944
    Abstract: A semiconductor device includes a substrate, a logic circuit provided on the substrate, a wiring layer including a plurality of wirings that are provided above the logic circuit, a first insulating film below the wiring layer, a plug, and a second insulating film. Each of the wirings contains copper and extends along a surface plane of the substrate in a first direction. The wirings are arranged along the surface plane of the substrate in a second direction different from the first direction. The plug extends through the first insulating film in a third direction crossing the first and second directions and is electrically connected to one of the wirings. The plug contains tungsten. The second insulating film is provided between the first insulating film and the plug.
    Type: Application
    Filed: February 25, 2020
    Publication date: March 18, 2021
    Inventors: Jun IIJIMA, Masayoshi TAGAMI, Masayuki KITAMURA, Satoshi WAKATSUKI
  • Publication number: 20200127007
    Abstract: A method of manufacturing a semiconductor device according to one embodiment includes forming a first film including a first metal above a processing target member. The method includes forming a second film including two or more types of element out of a second metal, carbon, and boron above the first film. The method includes forming a third film including the first metal above the second film. The method includes forming a mask film by providing an opening part to a stacked film including the first film, the second film and the third film. The method includes processing the processing target member by performing etching using the mask film as a mask.
    Type: Application
    Filed: December 18, 2019
    Publication date: April 23, 2020
    Applicant: TOSHIBA MEMORY CORPORATION
    Inventors: Ryohei KITAO, Atsuko SAKATA, Takeshi ISHIZAKI, Satoshi WAKATSUKI, Shinichi NAKAO, Shunsuke OCHIAI, Kei WATANABE
  • Publication number: 20200091088
    Abstract: In one embodiment, a semiconductor device includes a substrate, and a plurality of insulating layers provided on the substrate. The device further includes a plurality of electrode layers provided on the substrate alternately with the plurality of insulating layers and including metal atoms and impurity atoms different from the metal atoms, lattice spacing between the metal atoms in the electrode layers being greater than lattice spacing between the metal atoms in an elemental substance of the metal atoms.
    Type: Application
    Filed: March 7, 2019
    Publication date: March 19, 2020
    Applicant: TOSHIBA MEMORY CORPORATION
    Inventors: Satoshi WAKATSUKI, Masayuki KITAMURA, Atsuko SAKATA
  • Publication number: 20200091080
    Abstract: A semiconductor device includes a substrate. The semiconductor device further includes a wiring layer provided on the substrate, the wiring layer including a molybdenum layer including oxygen atoms as an impurity.
    Type: Application
    Filed: February 19, 2019
    Publication date: March 19, 2020
    Applicant: Toshiba Memory Corporation
    Inventors: Satoshi WAKATSUKI, Katsuaki NATORI
  • Publication number: 20200066750
    Abstract: A semiconductor storage device includes a semiconductor substrate; an insulating layer provided on the semiconductor substrate; a barrier metal layer provided on the insulating layer; an aluminum compound layer provided on the barrier metal layer; an amorphous layer provided on the aluminum compound layer and including a material that vaporizes upon its chemical reaction with fluorine; and a metal layer provided on the amorphous layer.
    Type: Application
    Filed: February 27, 2019
    Publication date: February 27, 2020
    Applicant: TOSHIBA MEMORY CORPORATION
    Inventors: Kensei TAKAHASHI, Takashi ASANO, Satoshi WAKATSUKI
  • Patent number: 10566280
    Abstract: In one embodiment, a semiconductor device includes a first insulator. The device further includes a metal layer that includes a first metal layer provided on a surface of the first insulator, and a second metal layer provided on a surface of the first metal layer and containing a first metallic element and oxygen or containing aluminum and nitrogen, or includes a third metal layer provided on the surface of the first insulator and containing a second metallic element, aluminum and nitrogen. The device further includes an interconnect material layer provided on a surface of the metal layer.
    Type: Grant
    Filed: August 14, 2018
    Date of Patent: February 18, 2020
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Satoshi Wakatsuki, Masayuki Kitamura, Takeshi Ishizaki, Hiroshi Itokawa, Daisuke Ikeno, Kei Watanabe, Atsuko Sakata
  • Patent number: 10541250
    Abstract: A method of manufacturing a semiconductor device according to one embodiment includes forming a first film including a first metal above a processing target member. The method includes forming a second film including two or more types of element out of a second metal, carbon, and boron above the first film. The method includes forming a third film including the first metal above the second film. The method includes forming a mask film by providing an opening part to a stacked film including the first film, the second film and the third film. The method includes processing the processing target member by performing etching using the mask film as a mask.
    Type: Grant
    Filed: June 28, 2016
    Date of Patent: January 21, 2020
    Assignee: Toshiba Memory Corporation
    Inventors: Ryohei Kitao, Atsuko Sakata, Takeshi Ishizaki, Satoshi Wakatsuki, Shinichi Nakao, Shunsuke Ochiai, Kei Watanabe
  • Publication number: 20190279932
    Abstract: In one embodiment, a semiconductor device includes a first insulator. The device further includes a metal layer that includes a first metal layer provided on a surface of the first insulator, and a second metal layer provided on a surface of the first metal layer and containing a first metallic element and oxygen or containing aluminum and nitrogen, or includes a third metal layer provided on the surface of the first insulator and containing a second metallic element, aluminum and nitrogen. The device further includes an interconnect material layer provided on a surface of the metal layer.
    Type: Application
    Filed: August 14, 2018
    Publication date: September 12, 2019
    Applicant: TOSHIBA MEMORY CORPORATION
    Inventors: Satoshi WAKATSUKI, Masayuki KITAMURA, Takeshi ISHIZAKI, Hiroshi ITOKAWA, Daisuke IKENO, Kei WATANABE, Atsuko SAKATA
  • Publication number: 20190259621
    Abstract: A production method of a semiconductor device includes introducing a reduction gas for reducing metal to a space containing a target to be used as the semiconductor device. The method also includes introducing a material gas and a first gas simultaneously to the space on a basis of a predetermined partial pressure ratio after introducing the reduction gas, to form a film that contains the metal, on the target. The material gas etches the metal when only the material gas is flowed. The first gas is different from the material gas. The predetermined partial pressure ratio is a ratio of the material gas and the first gas.
    Type: Application
    Filed: July 10, 2018
    Publication date: August 22, 2019
    Applicant: TOSHIBA MEMORY CORPORATION
    Inventors: Katsuaki NATORI, Satoshi WAKATSUKI, Masayuki KITAMURA
  • Patent number: 10312255
    Abstract: According to one embodiment, the plurality of charge storage films are separated in a stacking direction with a second air gap interposed. The plurality of insulating films are provided on side surfaces of electrode layers opposing the charge storage films, on portions of surfaces of the electrode layers continuous from the side surfaces and opposing a first air gap between the electrode layers, and on corners of the electrode layers between the portions and the side surfaces. The plurality of insulating films are divided in the stacking direction with a third air gap interposed and without the charge storage films being interposed. The third air gap communicates with the first air gap and the second air gap between the first air gap and the second air gap.
    Type: Grant
    Filed: November 1, 2017
    Date of Patent: June 4, 2019
    Assignee: Toshiba Memory Corporation
    Inventors: Yasuhito Yoshimizu, Satoshi Wakatsuki, Yohei Sato, Keiichi Sawa
  • Patent number: 10269825
    Abstract: According to one embodiment, a stacked body includes a plurality of metal layers stacked with an insulator interposed. A semiconductor body extends in a stacking direction through the stacked body. A charge storage portion is provided between the semiconductor body and one of the metal layers. A metal nitride film has a first portion and a second portion. The first portion is provided between the charge storage portion and one of the metal layers. The second portion is thicker than the first portion and is provided between one of the metal layers and the insulator.
    Type: Grant
    Filed: September 7, 2016
    Date of Patent: April 23, 2019
    Assignee: Toshiba Memory Corporation
    Inventors: Satoshi Wakatsuki, Atsuko Sakata, Daisuke Ikeno
  • Patent number: 10170494
    Abstract: According to one embodiment, a semiconductor device includes an underlying metal film and a metal film. The underlying metal film is a tantalum-aluminum film having an aluminum content of more than 50 atomic % and less than 85 atomic %, a tungsten-zirconium film having a zirconium content of less than 40 atomic %, a tungsten-titanium film having a titanium content of less than 80 atomic %, or a tungsten film. The metal film is provided on the underlying metal film and in contact with the underlying metal film. The metal film contains at least one of tungsten and molybdenum, and has a main orientation of (100) or (111).
    Type: Grant
    Filed: February 19, 2016
    Date of Patent: January 1, 2019
    Assignee: Toshiba Memory Corporation
    Inventors: Takeshi Ishizaki, Atsuko Sakata, Satoshi Wakatsuki
  • Publication number: 20180277667
    Abstract: A semiconductor device includes first and second electrodes, first semiconductor region of first conductivity type between the first and second electrodes, a second semiconductor region of second conductivity type between the first semiconductor region and the first electrode, a third semiconductor region of the second conductivity type between the first semiconductor region and the second electrode, a fourth semiconductor region of the first conductivity type between the third semiconductor region and the second electrode, a plurality of third electrodes between the second electrode and the first semiconductor region, wherein a gate insulating film is between each third electrode and the third semiconductor region, a fourth electrode extending between the third semiconductor region and the second electrode and electrically connected to the third semiconductor region and the second electrode, and a first insulating film between the second and electrodes.
    Type: Application
    Filed: August 29, 2017
    Publication date: September 27, 2018
    Inventors: Hideki SEKIGUCHI, Keiko KAWAMURA, Kaori FUSE, Akira KOMATSU, Ryohei KITAO, Satoshi WAKATSUKI, Atsuko SAKATA, Koichi KUBO
  • Publication number: 20180274092
    Abstract: A semiconductor manufacturing apparatus includes a reaction chamber configured to perform a process on a semiconductor substrate using a gas mixture comprising a first gas, and a first path configured to exhaust resultant gas that comprises the first gas from the reaction chamber. The semiconductor manufacturing apparatus further includes a first trap provided in the first path and configured to extract at least a portion of the first gas from the resultant gas, and a second path in which the trap is not provided and configured to exhaust the resultant gas from the reaction chamber.
    Type: Application
    Filed: September 5, 2017
    Publication date: September 27, 2018
    Applicant: TOSHIBA MEMORY CORPORATION
    Inventors: Masayuki KITAMURA, Atsuko SAKATA, Satoshi WAKATSUKI
  • Patent number: 9997533
    Abstract: According to one embodiment, the plurality of charge storage films are separated in a stacking direction with a second air gap interposed. The plurality of insulating films are provided on side surfaces of electrode layers opposing the charge storage films, on portions of surfaces of the electrode layers continuous from the side surfaces and opposing a first air gap between the electrode layers, and on corners of the electrode layers between the portions and the side surfaces. The plurality of insulating films are divided in the stacking direction with a third air gap interposed and without the charge storage films being interposed. The third air gap communicates with the first air gap and the second air gap between the first air gap and the second air gap.
    Type: Grant
    Filed: March 15, 2016
    Date of Patent: June 12, 2018
    Assignee: Toshiba Memory Corporation
    Inventors: Yasuhito Yoshimizu, Satoshi Wakatsuki, Yohei Sato, Keiichi Sawa
  • Patent number: 9911753
    Abstract: According to one embodiment, an insulating layer is provided above a stairstep portion of a stacked body. A first cover film is provided between the stairstep portion and the insulating layer. The first cover film is of a material different from the insulating layer. A separation portion divides the stacked body and the insulating layer. A second cover film is provided at a side surface of the insulating layer on the separation portion side. The second cover film is of a material different from the insulating layer.
    Type: Grant
    Filed: September 6, 2016
    Date of Patent: March 6, 2018
    Assignee: Toshiba Memory Corporation
    Inventors: Masayuki Kitamura, Atsuko Sakata, Satoshi Wakatsuki, Takeshi Ishizaki, Daisuke Ikeno, Tomotaka Ariga
  • Patent number: 9905462
    Abstract: According to one embodiment, the stacked body includes a plurality of metal films, a plurality of silicon oxide films, and a plurality of intermediate films. The intermediate films are provided between the metal films and the silicon oxide films. The intermediate films contain silicon nitride. Nitrogen composition ratios of the intermediate films are higher on sides of interfaces between the intermediate films and the metal films than on sides of interfaces between the intermediate films and the silicon oxide films. Silicon composition ratios of the intermediate films are higher on sides of interfaces between the intermediate films and the silicon oxide films than on sides of interfaces between the intermediate films and the metal films.
    Type: Grant
    Filed: December 31, 2015
    Date of Patent: February 27, 2018
    Assignee: Toshiba Memory Corporation
    Inventors: Atsuko Sakata, Takeshi Ishizaki, Shinya Okuda, Kei Watanabe, Masayuki Kitamura, Satoshi Wakatsuki, Daisuke Ikeno, Junichi Wada, Hirotaka Ogihara