Abstract: Various techniques are provided to implement fast boot for programmable logic devices (PLDs). In one example, a method includes receiving configuration data associated with a PLD. The PLD includes an array of configuration memory cells including logic block memory cells and input/output (I/O) block memory cells associated with the PLD's logic fabric and I/O fabric, respectively. The method further includes programming a subset of the I/O block memory cells with the configuration data, and providing a wakeup signal to activate functionality associated with a portion of the I/O fabric. The method further includes programming remaining configuration memory cells of the array with the configuration data, where the remaining configuration memory cells include at least a subset of the logic block memory cells. The method further includes providing a wakeup signal to activate functionality associated with at least a portion of the logic fabric. Related systems and devices are provided.

Abstract: Various techniques are provided to implement look-up table (LUT) circuits. In one example, a LUT circuit includes a first LUT configured to selectively receive a first input signal and each input signal of a set of input signals and determine a first output signal based on the first input signal and/or an input signal(s) of the set. The LUT circuit also includes a second LUT configured to selectively receive a second input signal and each input signal of the set and determine a second output signal based on the second input signal and/or an input signal(s) of the set. The LUT circuit also includes a multiplexer configured to selectively receive the first and second output signals and a third input signal, and selectively provide, based on the third input signal, the first or second output signal as an output of the LUT circuit. Related systems and methods are also provided.

Abstract: Systems and methods for management of remotely programmable, programmable logic devices (remote PLDs) are disclosed. An example system includes a remote PLD including a plurality of programmable logic blocks (PLBs) arranged in a PLD fabric and a programmable input/output (I/O) coupled to the PLD fabric. The remote PLD is configured to form a communications link between the remote PLD and a remote PLD management system node over a communications network via a communication module of the remote PLD or a host device configured to interface with the remote PLD over the programmable I/O. The remote PLD is configured to receive a protected configuration image from the remote PLD management system node over the communications link and programs the PLD fabric according to the protected configuration image.

Abstract: Various techniques are provided to implement fast boot for programmable logic devices (PLDs). In one example, a method includes receiving configuration data associated with a PLD. The PLD includes an array of configuration memory cells including logic block memory cells and input/output (I/O) block memory cells associated with the PLD's logic fabric and I/O fabric, respectively. The method further includes programming a subset of the I/O block memory cells with the configuration data, and providing a wakeup signal to activate functionality associated with a portion of the I/O fabric. The method further includes programming remaining configuration memory cells of the array with the configuration data, where the remaining configuration memory cells include at least a subset of the logic block memory cells. The method further includes providing a wakeup signal to activate functionality associated with at least a portion of the logic fabric. Related systems and devices are provided.

Abstract: Various techniques are provided to implement fast boot for programmable logic devices (PLDs). In one example, a method includes receiving configuration data associated with a PLD. The PLD includes an array of configuration memory cells including logic block memory cells and input/output (I/O) block memory cells associated with the PLD's logic fabric and I/O fabric, respectively. The method further includes programming a subset of the I/O block memory cells with the configuration data, and providing a wakeup signal to activate functionality associated with a portion of the I/O fabric. The method further includes programming remaining configuration memory cells of the array with the configuration data, where the remaining configuration memory cells include at least a subset of the logic block memory cells. The method further includes providing a wakeup signal to activate functionality associated with at least a portion of the logic fabric. Related systems and devices are provided.

Abstract: Systems and methods are described for dynamically managing a hazard. Systems and methods are described for monitoring a location of a hazard and predicting its movement based on received information about the hazard and known information about the site where the hazard is located. Users can be directed or redirected based on the hazard or incident and the need to contain the hazard while providing coverage on previously assigned patrol routes. The information can be used to learn what occurred at a hazard and update patrol routes and instructions for users when responding to an incident, and to predict future hazard movement.

Abstract: Various techniques are provided to implement fast boot for programmable logic devices (PLDs). In one example, a method includes receiving configuration data associated with a PLD. The PLD includes an array of configuration memory cells including logic block memory cells and input/output (I/O) block memory cells associated with the PLD's logic fabric and I/O fabric, respectively. The method further includes programming a subset of the I/O block memory cells with the configuration data, and providing a wakeup signal to activate functionality associated with a portion of the I/O fabric. The method further includes programming remaining configuration memory cells of the array with the configuration data, where the remaining configuration memory cells include at least a subset of the logic block memory cells. The method further includes providing a wakeup signal to activate functionality associated with at least a portion of the logic fabric. Related systems and devices are provided.

Abstract: Various implementations of a digital signal processing (DSP) block architecture of a programmable logic device (PLD) and related methods are provided. In one example, a PLD includes a dedicated DSP block. The DSP block includes a first multiplier adapted to multiply a first plurality of input signals to provide a first plurality of product signals. The DSP block also includes a second multiplier adapted to multiply a second plurality of input signals to provide a second plurality of product signals. The DSP block further includes an arithmetic logic unit (ALU) adapted to operate on the first product signals and the second product signals received at first and second operand inputs, respectively, of the ALU to provide a plurality of output signals.

Abstract: In one embodiment, a programmable logic device includes a plurality of configuration cells that store configuration data, wherein the programmable logic device is adapted to provide soft error upset (SEU) protection for the configuration cells that are reprogrammable. The programmable logic device may further include or alternatively provide hard coding and/or hard encoding of the configuration cells.

Abstract: In one embodiment, a programmable logic device includes a plurality of configuration memory cells and at least one spare configuration memory cell adapted to store configuration data for a memory cell identified within the plurality of configuration memory cells (e.g., identified as a defective memory cell). An address shift register within the device is adapted to provide programming signals to the plurality of configuration memory cells via wordlines. A data shift register within the device is adapted to provide configuration data to the plurality of configuration memory cells via bitlines. The data shift register is further adapted to provide configuration data from the spare configuration memory cell to the identified configuration memory cell.

Abstract: In one embodiment, a programmable logic device includes a plurality of configuration cells that store configuration data, wherein the programmable logic device is adapted to provide soft error upset (SEU) protection for the configuration cells that are reprogrammable. The programmable logic device may further include or alternatively provide hard coding and/or hard encoding of the configuration cells.

Abstract: In one embodiment, an integrated circuit (IC) such as a programmable logic device includes a plurality of IC input terminals and an input buffer having a buffer input terminal and a buffer output terminal. A multiplexer is adapted to selectively couple an IC input terminal to the buffer input terminal or to couple the buffer output terminal to the buffer input terminal.

Abstract: Systems and methods are disclosed directed to techniques with respect to defective configuration memory cells. For example, in accordance with an embodiment of the present invention, a programmable logic device includes a plurality of configuration memory cells; and at least one spare memory cell, wherein the at least one spare memory cell is adapted to store configuration data to provide to at least one defective configuration memory cell.

Abstract: A programmable logic block within a programmable logic device includes at least two interconnected slices, each of the interconnect slices including at least two interconnected lookup tables. Each interconnected lookup table is adapted to receive input signals from a routing structure and to provide a LUT output signal. At least one of the slices includes a register adapted to register the LUT output signal of a lookup table and at least another of the slices includes fewer such registers than lookup tables.

Abstract: A programmable logic device, in accordance with an embodiment, includes a first terminal; an input buffer having a buffer input terminal and a buffer output terminal; and a multiplexer coupled to the first terminal and to the input buffer, wherein the multiplexer is adapted to selectively couple either the first terminal to the buffer input terminal or couple the buffer output terminal to the buffer input terminal.

Abstract: A burn-in test system. A burn-in test system includes a device under test (DUT), a temperature controller coupled to the DUT, and a test controller. During testing, the test controller: (a) sets a parameter of the DUT to a first value and applies a test stimulus to the DUT, and (b) sets the parameter of the DUT to a second value and applies the test stimulus to the DUT. A change in the value of the parameter results in a change in the amount of heat dissipated by the DUT. The temperature controller maintains the DUT at a pre-determined temperature during testing with the parameter set to both the first and the second values. The DUT may be further coupled to a module that comprises circuitry employed in a product-level application environment. The module is configured by the test controller to simulate a product-level application.

Abstract: Systems and methods are disclosed directed to techniques with respect to defective configuration memory cells. For example, in accordance with an embodiment of the present invention, a programmable logic device includes a plurality of configuration memory cells; and at least one spare memory cell, wherein the at least one spare memory cell is adapted to store configuration data to provide to at least one defective configuration memory cell.

Abstract: In one embodiment, a programmable logic device is provided that includes a memory having memory cells, each memory cell operable to store either a configuration bit or a RAM bit; a masking circuit operable to mask a RAM bit by providing a masking value for the masked RAM bit; an error detection circuit operable to process the configuration bits during operation of the programmable logic device using an error detection algorithm, the error detection circuit calculating a signature that includes configuration bits and masking values; and a comparator operable to compare the signature calculated by the error detection circuit with a correct signature.

Abstract: In one embodiment of the invention, a programmable logic device such as an FPGA includes a programmable fabric; a JTAG interface operable to receive configuration data for programming the fabric; a SPI interface operable to receive and transmit configuration data for programming the fabric; and circuitry coupled to the JTAG and SPI interfaces. The circuitry is operable, without being configured, to transfer configuration data received at the JTAG interface to the SPI interface for transmission to an external device having a SPI interface, such as a serial flash memory.

Abstract: Systems and methods are disclosed herein to provide improved alignment of output signals of an analog-to-digital converter (ADC). For example, in accordance with an embodiment of the present invention, a method of aligning digital signals appearing on signal paths of a parallel data bus includes sampling the digital signals at a plurality of delay times to obtain a plurality of sample sets, wherein each sample set is associated with a corresponding delay time. A second digital signal that is misaligned with respect to a first digital signal is identified from the sample sets. The delay time required to align the second digital signal with the first digital signal is determined. The delay of the second digital signal is adjusted by the determined delay time.