Abstract: A field-programmable gate array (FPGA) having at least one programmable cell (e.g., an input/output (I/O) cell) having an output node circuit (e.g., a pad circuit) in which the output data signal and the tri-state signal are applied to a multiplexer that drives the tri-state port of an output buffer in the output node circuit. This configuration enables the output node circuit to be configured for open drain drive mode operations in a fast, predictable manner that does not need to rely on the FPGA's general routing resources.

Abstract: A single integrated circuit (IC) having one or more regions of mask-programmed device (MPD) logic for implementing permanent functions and one or more regions of field-programmable gate-array (FPGA) logic for implementing user-specified functions. The FPGA-type logic provides programming flexibility, while the MPD-type logic provides size, speed, functionality, and dollar cost advantages. In one embodiment, a hybrid IC has an array of programmable logic cells (PLCs) implemented using FPGA-type logic, an application-specific block (ASB) implemented using MPD-type logic, and a ring of pads. Fast interface switch hierarchy (FISH) cells provide the interface between the PLC array and the pads, between the PLC array and the ASB, and between the ASB and the pad ring.

Abstract: The bi-directional (BI-DI) buffers and supplemental logic and interconnect (SLIC) cells are designed to be programmed to operate in different modes in order to implement different kinds of logic circuits. In particular, BI-DI buffers of the present invention support at least five different operational modes. In a first mode (Mode A), the BI-DI buffer generates a logic "1" output, for any input value. In a second mode (Mode B), the BI-DI buffer generates a logic "0" output, for any input value. In a third mode (Mode C), the BI-DI buffer buffers the input signal and generates an output signal equal to the input signal. In a fourth mode (Mode D), the BI-DI buffer buffers the input signal and generates an output signal equal to the inverse of the input signal. In a fifth mode, (Mode E), the BI-DI buffer operates as a conventional tri-state driver. Two or more of the BI-DI buffers can be configured to form more complex logic circuits having two or more inputs.

Abstract: A field programmable gate array includes programmable function units (PFUs) that may function as either a logic block or a random access memory (RAM). Each PFU has a write-port enable input when the PFUs are being used as user RAM units. In addition, each PFU includes a write-strobe input. The write operation is accomplished when both the write-port enable input and the write-strobe input are active. This technique allows a reduction of logic gates and control signal conductors. In many cases, these advantages allow for higher system operating frequencies and more gate capacity at a lower cost.

Abstract: A field programmable gate array (FPGA) includes at least one programmable function unit (PFU) which comprises input lines, output lines, and a look-up table (LUT) for generating various functions in response to a configuration bit stream. A first function is an adder/subtracter in which the first input line provides an add/subtract control signal to a multiplexer coupled to a full-adder. The multiplexer determines whether a data bit or its complement is coupled to the full-adder. A second function is an AND gate coupled to the full-adder in which the first input line provides a data bit to the AND gate. The second function provides a basic cell for a parallel multiplier. Furthermore, the first input line may be used as a control line or a data line for a general logic function, depending on the PFU function.

Abstract: A field programmable gate array (FPGA) with a programmable function unit (PFU) that includes a look-up table (LUT) for implementing a plurality of functions including first and second RAM cells, and a programmable switching device dedicated to coupling and decoupling the RAM cells. The first and second RAM cells are coupled to respective first and second read/write ports. The RAM cells function individually as single-port RAM cells when decoupled by the switching device. However, the RAM cells share data to function collectively as a dual-port RAM cell when coupled by the switching device. The dual-port RAM cell is accessible by both the first and second read/write ports.