Patents by Inventor Satya N. Yedidi

Satya N. Yedidi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10402932
    Abstract: An embodiment of an electronic processing system may include an application processor, persistent storage media communicatively coupled to the application processor, a graphics subsystem communicatively coupled to the application processor, a power budget analyzer to identify a power budget for one or more of the application processor, the persistent storage media, and the graphics subsystem, a target analyzer communicatively coupled to the graphics subsystem to identify a target for the graphics subsystem, and a parameter adjuster to adjust one or more parameters of the graphics subsystem based on one or more of the identified power budget and the identified target.
    Type: Grant
    Filed: April 17, 2017
    Date of Patent: September 3, 2019
    Assignee: Intel Corporation
    Inventors: Abhishek R. Appu, Stanley J. Baran, Sang-Hee Lee, Atthar H. Mohammed, Jong Dae Oh, Hiu-Fai R. Chan, Jill M. Boyce, Fangwen Fu, Satya N. Yedidi, Sumit Mohan, James M. Holland, Keith W. Rowe, Altug Koker
  • Publication number: 20190261001
    Abstract: A system for video encoding is described herein. The system includes a processor to execute a multi-pass palette search and mapping on a video frame to generate palette candidates. The processor is to execute an intra block copy prediction on the video frame to generate intra-block-copy candidates. The processor is to also calculate a rate distortion optimization (RDO) cost for a set of generated residuals, the palette candidates, and the intra-block-copy candidates. The processor is to further also execute a final mode decision based on a comparison of the rate distortion optimization (RDO) costs.
    Type: Application
    Filed: May 1, 2019
    Publication date: August 22, 2019
    Applicant: INTEL CORPORATION
    Inventors: James M. Holland, Srinivasan Embar Raghukrishnan, Dmitry E. Ryzhov, Lidong Xu, Satya N. Yedidi, Wenhao Zhang
  • Publication number: 20190228544
    Abstract: A system includes a camera to capture real world content and a semiconductor package apparatus. The semiconductor package apparatus includes a substrate and logic. The logic includes a graphics pipeline to generate rendered content, a base layer encoder to encode real world content into a base layer and a first layer encoder to encode rendered content into a first non-base layer, a multiplexer to interleave the base layer with the first non-base layer to obtain a single output signal having mixed reality content, and a transmitter to transmit the single output signal. The system further includes a second layer encoder to encode map data into a second non-base layer. The multiplexer to interleave the second non-base layer with the first non-base layer and the base layer. The first and second layer encoders encode the rendered content and the map data into overlay auxiliary pictures.
    Type: Application
    Filed: January 28, 2019
    Publication date: July 25, 2019
    Inventors: Jill M. Boyce, Keith W. Rowe, James M. Holland, Fangwen Fu, Satya N. Yedidi, Sumit Mohan
  • Patent number: 10291925
    Abstract: An apparatus of video encoding is described herein. The apparatus includes an encoder and a hardware bit packing unit. The encoder includes a fixed function hierarchical motion estimation search unit, fixed function integer motion estimation search units, and a fixed function check and refinement unit. The check and refinement unit is to generate residuals using nested loops based on at least one spatial domain prediction and at least one frequency domain prediction and perform a final mode decision based on rate distortion optimization (RDO) costs associated with the generated residuals. The hardware bit packing unit is to pack bits as coded according to the final mode decision into a data format.
    Type: Grant
    Filed: July 28, 2017
    Date of Patent: May 14, 2019
    Assignee: Intel Corporation
    Inventors: James M. Holland, Srinivasan Embar Raghukrishnan, Lidong Xu, Fangwen Fu, Dmitry E. Ryzhov, Satya N. Yedidi
  • Publication number: 20190042177
    Abstract: In one aspect, an apparatus comprises an encoder configured to encode groups of pixels of a video frame into encoded groups. The video frame comprises a plurality of tiles and each of the plurality of tiles comprises one or more of the groups. For each tile in the plurality of tiles: the encoder is configured to generate a notification based on completion of encoding an encoded tile corresponding to the tile. The apparatus comprises a packetizer configured to generate packets corresponding to the video frame simultaneous with the encoding of the video frame by the encoder. For each tile in the plurality of tiles: the packetizer is configured to generate packets from the encoded tile corresponding to the tile based on the notification.
    Type: Application
    Filed: January 10, 2018
    Publication date: February 7, 2019
    Inventors: Jason Tanner, Arthur Jeremy Runyan, Satya N. Yedidi, Changliang Wang, Ankur Shah, Paul S. Diefenbaugh
  • Publication number: 20190045196
    Abstract: Speeding up small block intra-prediction in video coding is described herein. The system includes an encoder. The encoder is to execute intra-prediction by deriving a plurality of prediction angles, wherein the prediction angles are based on a video coding standard. The encoder is also to disable a prediction angle for a current block to eliminate a dependency on an immediate predecessor block.
    Type: Application
    Filed: June 22, 2018
    Publication date: February 7, 2019
    Applicant: INTEL CORPORATION
    Inventors: Zhijun LEI, Jason TANNER, Satya N. YEDIDI
  • Publication number: 20190037227
    Abstract: An apparatus of video encoding is described herein. The apparatus includes an encoder and a hardware bit packing unit. The encoder includes a fixed function hierarchical motion estimation search unit, fixed function integer motion estimation search units, and a fixed function check and refinement unit. The check and refinement unit is to generate residuals using nested loops based on at least one spatial domain prediction and at least one frequency domain prediction and perform a final mode decision based on rate distortion optimization (RDO) costs associated with the generated residuals. The hardware bit packing unit is to pack bits as coded according to the final mode decision into a data format.
    Type: Application
    Filed: July 28, 2017
    Publication date: January 31, 2019
    Applicant: Intel Corporation
    Inventors: James M. Holland, Srinivasan Embar Raghukrishnan, Lidong Xu, Fangwen Fu, Dmitry E. Ryzhov, Satya N. Yedidi
  • Publication number: 20190028710
    Abstract: The present techniques include deriving a threshold to maintain an encoding bitrate and determining a percentage of change of a current frame N based on an impact to a bitrate budget. The present techniques also include marking a reference frame N?1 as non-referenceable in response to the percentage of change being smaller than the threshold and encoding a static portion of frame N as a skip and encoding a non-static portion of frame N by referencing the reference frame N?1. Finally, the present techniques include overwriting a surface of the reference frame N with portions of the reference frame N?1 that have changed as compared to frame N.
    Type: Application
    Filed: November 17, 2017
    Publication date: January 24, 2019
    Applicant: INTEL CORPORATION
    Inventors: Fangwen Fu, Jason Tanner, Satya N. Yedidi
  • Publication number: 20180308257
    Abstract: A system includes a camera to capture real world content and a semiconductor package apparatus. The semiconductor package apparatus includes a substrate and logic. The logic includes a graphics pipeline to generate rendered content, a base layer encoder to encode real world content into a base layer and a first layer encoder to encode rendered content into a first non-base layer, a multiplexer to interleave the base layer with the first non-base layer to obtain a single output signal having mixed reality content, and a transmitter to transmit the single output signal. The system further includes a second layer encoder to encode map data into a second non-base layer. The multiplexer to interleave the second non-base layer with the first non-base layer and the base layer. The first and second layer encoders encode the rendered content and the map data into overlay auxiliary pictures.
    Type: Application
    Filed: April 24, 2017
    Publication date: October 25, 2018
    Inventors: Jill M. Boyce, Keith W. Rowe, James M. Holland, Fangwen Fu, Satya N. Yedidi, Sumit Mohan
  • Publication number: 20180300839
    Abstract: An embodiment of an electronic processing system may include an application processor, persistent storage media communicatively coupled to the application processor, a graphics subsystem communicatively coupled to the application processor, a power budget analyzer to identify a power budget for one or more of the application processor, the persistent storage media, and the graphics subsystem, a target analyzer communicatively coupled to the graphics subsystem to identify a target for the graphics subsystem, and a parameter adjuster to adjust one or more parameters of the graphics subsystem based on one or more of the identified power budget and the identified target.
    Type: Application
    Filed: April 17, 2017
    Publication date: October 18, 2018
    Inventors: Abhishek R. Appu, Stanley J. Baran, Sang-Hee Lee, Atthar H. Mohammed, Jong Dae Oh, Hiu-Fai R. Chan, Jill M. Boyce, Fangwen Fu, Satya N. Yedidi, Sumit Mohan, James M. Holland, Keith W. Rowe, Altug Koker
  • Publication number: 20180288435
    Abstract: An embodiment of an electronic processing system may include a 2D frame which corresponds to a projection of a 360 video space, and a component predictor to predict an encode component for a first block of a 2D frame based on encode information from a neighboring block which is neighboring to the first block of the 2D frame only in the 360 video space, a prioritizer to prioritize transmission for a second block of the 2D frame based on an identified region of interest, and/or a format detector to detect a 360 video format of the 2D frame based on image content. A 360 video capture device may include a contextual tagger to tag 360 video content with contextual information which is contemporaneous with the captured 360 video content. Other embodiments are disclosed and claimed.
    Type: Application
    Filed: April 1, 2017
    Publication date: October 4, 2018
    Applicant: Intel Corporation
    Inventors: Jill M. Boyce, Sang-Hee Lee, Abhishek R. Appu, Wen-Fu Kao, Joydeep Ray, Ya-Ti Peng, Keith W. Rowe, Fangwen Fu, Satya N. Yedidi, Sumit Mohan, James M. Holland
  • Publication number: 20180041770
    Abstract: An apparatus of video encoding is described herein. The apparatus includes an encoder and a hardware bit packing unit. The encoder comprises at least a fixed function dual hierarchical motion estimation search units, dual integer motion estimation search units, and a fractional motion estimation search unit. Moreover, the hardware bit packing unit is to pack bits as coded according to the final macroblock coding decision into a data format.
    Type: Application
    Filed: April 10, 2017
    Publication date: February 8, 2018
    Applicant: INTEL CORPORATION
    Inventors: James M. Holland, Fangwen Fu, Satya N. Yedidi, Srinivasan Embar Raghukrishnan
  • Patent number: 9609315
    Abstract: Iterative video encoding systems, methods and computer program products, where residue quantization and data packing operations of an encoding process may he repeated with various values for a quantization parameter, without repeating the determination of macroblock prediction codes. In an embodiment, the size of an actual file generated by encoding is compared to a target file size. The QP may be adjusted depending on the amount by which these file sizes differ. The quantization and packing may then be repeated with the adjusted QP. In an embodiment, a greater difference in these file sizes results in a greater adjustment to the QP.
    Type: Grant
    Filed: November 14, 2011
    Date of Patent: March 28, 2017
    Assignee: Intel Corporation
    Inventors: Ning Lu, Hong Jiang, Atthar H. Mohammed, Satya N. Yedidi
  • Patent number: 9363513
    Abstract: A sequence of encoded data associated with a block of video is assessed to determine if: quantized coefficients of transformed residual pixel data associated with the block are equal to zero, the block was encoded using a temporal compression process, a slice that includes the block is configured to be encoded using only one reference picture list or two reference picture lists, the block is unpartitioned or was encoded in direct mode, a reference picture used to encode the block is the reference picture associated with a lowest index value on the one reference picture list, and an actual motion vector associated with the block is equal to a predicted motion vector associated with the block.
    Type: Grant
    Filed: December 14, 2011
    Date of Patent: June 7, 2016
    Assignee: Intel Corporation
    Inventors: Satya N. Yedidi, Atthar H. Mohammed, Hong Jiang, Ning Lu
  • Publication number: 20140219354
    Abstract: A sequence of encoded data associated with a block of video is assessed to determine if: quantized coefficients of transformed residual pixel data associated with the block are equal to zero, the block was encoded using a temporal compression process, a slice that includes the block is configured to be encoded using only one reference picture list or two reference picture lists, the block is unpartitioned or was encoded in direct mode, a reference picture used to encode the block is the reference picture associated with a lowest index value on the one reference picture list, and an actual motion vector associated with the block is equal to a predicted motion vector associated with the block.
    Type: Application
    Filed: December 14, 2011
    Publication date: August 7, 2014
    Inventors: Satya N. Yedidi, Atthar H. Mohammed, Hong Jiang, Ning Lu
  • Publication number: 20140086338
    Abstract: Systems and methods for the insertion of metadata in a video encoding system, without software intervention. Header data may be provided to hardware circuitry, which may then construct and format one or more headers to accommodate the header data. The header data may then be appended to the encoded video. The combination of the header data and the encoded video may then be multiplexed with audio data and/or user data, and encrypted if necessary.
    Type: Application
    Filed: December 28, 2011
    Publication date: March 27, 2014
    Inventors: Ning Lu, Atthar H. Mohammed, Satya N. Yedidi, Ping Liu
  • Publication number: 20130272392
    Abstract: Iterative video encoding systems, methods and computer program products, where residue quantization and data packing operations of an encoding process may he repeated with various values for a quantization parameter, without repeating the determination of macroblock prediction code. In an embodiment, the size of an actual file generated by encoding is compared to a target file size. The QP may be adjusted depending on the amount by which these file sizes differ. The quantization and packing may then be repeated with the adjusted QP. In an embodiment, a greater difference in these file sizes results in a greater adjustment to the QP.
    Type: Application
    Filed: November 14, 2011
    Publication date: October 17, 2013
    Inventors: Ning Lu, Hong Jiang, Atthar H. Mohammed, Satya N. Yedidi