Patents by Inventor Satya Prakash

Satya Prakash has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7939061
    Abstract: The invention relates to immobilized or encapsulated enzyme and/or cells to lower bile acids and cholesterol. The invention also relates to methods of quantitatively measuring bile acids. The invention provides a composition for decreasing the amount of a target compound in the gastrointestinal tract of an animal, comprising: a) a biologically active agent which decreases the amount of the target compound; b) a retainer for retaining the biologically active agent by contacting the agent to limit movement of the agent; and c) a carrier.
    Type: Grant
    Filed: March 1, 2004
    Date of Patent: May 10, 2011
    Assignee: Micropharma Limited
    Inventors: Satya Prakash, Mitchell Lawrence Jones
  • Publication number: 20110107054
    Abstract: A method, system, and computer usable program product for expanding memory size are provided in the illustrative embodiments. A desired size of an expanded memory and a first information about a workload in the data processing system are received. A size of a compressed memory pool to use with the memory to make the desired size of the expanded memory available is computed. A representation of the memory is configured, the representation of the memory appearing to be of a size larger than the size of the memory, the representation of the memory being the expanded memory, and the size of the representation being the size of the expanded memory. The expanded memory is made available such that the memory in the data processing system is usable by addressing the expanded memory.
    Type: Application
    Filed: November 3, 2009
    Publication date: May 5, 2011
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: David Alan Hepkin, Satya Prakash Sharma, Saurabh Nath Sharma, Randal Craig Swanberg
  • Publication number: 20110104240
    Abstract: The present disclosure provides a device having a casing with a barrier surface and a contact surface and a composition in the casing having a nitric oxide precursor and an isolated enzyme or live cell expressing an endogenous enzyme, for converting the nitric oxide gas precursor to nitric oxide gas or having activity on a substrate that produces a catalyst that causes the conversion of the nitric oxide gas precursor to nitric oxide gas. The present disclosure also provides methods and uses for treating wounds, microbial infections and dermatological disorders and for preserving meat products.
    Type: Application
    Filed: June 23, 2009
    Publication date: May 5, 2011
    Applicant: Micropharma Limited
    Inventors: Mitchell Lawrence Jones, Satya Prakash
  • Publication number: 20110106000
    Abstract: The present disclosure provides a device having a casing with a barrier surface and a contact surface and a composition in the casing having a nitric oxide precursor and an isolated enzyme or live cell expressing an endogenous enzyme, for converting the nitric oxide gas precursor to nitric oxide gas or having activity on a substrate that produces a catalyst that causes the conversion of the nitric oxide gas precursor to nitric oxide gas. The present disclosure also provides compositions, methods and uses for skin cosmesis.
    Type: Application
    Filed: June 23, 2009
    Publication date: May 5, 2011
    Applicant: MICROPHARMA LIMITED
    Inventors: Mitchell Lawrence Jones, Satya Prakash
  • Publication number: 20110018930
    Abstract: An apparatus and method provide a protective coating (60) that extends within a feed slot (40) and is limited so as to not extend into a firing chamber (47).
    Type: Application
    Filed: April 30, 2008
    Publication date: January 27, 2011
    Inventors: Siddhartha Bhwomik, Lawrence H. White, Satya Prakash, Rio T. Rivas, Samuel Ajayi
  • Publication number: 20100215724
    Abstract: A nanotube device comprises a gel matrix that includes microcapsules and functionalized nanotubes, or other functionalized nanostructures incorporated into said gel matrix. Pharmaceutical compositions and methods of treatment comprising same. The pharmaceutical compositions of the present invention enable the specific and targeted delivery of therapeutic agents such as DNA molecules, peptides, including antibodies, drug molecules (e.g. small organic molecules), while offering sufficient resistance towards mucus layer of the intestine and high concentrations of enzymes and other molecules found in the blood stream and the GI tract.
    Type: Application
    Filed: November 22, 2006
    Publication date: August 26, 2010
    Inventors: Satya Prakash, Hongmei Chen, Pavan Raja, Omkaram Nalamasu, Pulickel M. Ajayan
  • Publication number: 20100074933
    Abstract: The invention relates to immobilized or encapsulated enzyme and/or cells to lower bile acids and cholesterol. The invention also relates to methods of quantitatively measuring bile acids. The invention provides a composition for decreasing the amount of a target compound in the gastrointestinal tract of an animal, comprising: a) a biologically active agent which decreases the amount of the target compound; b) a retainer for retaining the biologically active agent by contacting the agent to limit movement of the agent; and c) a carrier.
    Type: Application
    Filed: June 26, 2009
    Publication date: March 25, 2010
    Inventors: Satya Prakash, Mitchell Lawrence Jones
  • Patent number: 7669314
    Abstract: Methods for fabricating a printhead are described. In one embodiment, a method includes forming on a substrate using a single fabrication technique multiple resistors, some of the resistors to be used as heater resistors configured to eject fluid and some of the resistors to be used as storage resistors that store data, annealing the heater resistors, and intentionally not annealing at least one of the storage resistors, wherein the annealed storage resistors have a first state representing a first digital value and the unannealed storage resistors have a second state representing a second digital value, such that the values associated with the storage resistors can be read by an appropriate detection circuit.
    Type: Grant
    Filed: June 29, 2007
    Date of Patent: March 2, 2010
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: James A Feinn, Lawrence White, Satya Prakash, Donald W Schulte, Terry Mcmahon, Adam Ghozeil
  • Publication number: 20100047320
    Abstract: The present invention relates to an oral formulation to lower serum or hepatic lipid and triglyceride concentrations, hepatic inflammation and/or insulin resistance in a patient comprising live feruloyl esterase producing microorganisms alone or in association with a pharmaceutically acceptable carrier resistant to gastric conditions, and wherein the microorganisms are wild type, genetically modified, or combination thereof.
    Type: Application
    Filed: September 7, 2007
    Publication date: February 25, 2010
    Inventors: Satya Prakash, Jasmine Rohinton Bhathena
  • Publication number: 20100028449
    Abstract: The present invention relates to an oral formulation comprising a microcapsule containing bacteria and a fermented milk carrier. There is also provided a method of medical treatment of an inflammatory gastrointestinal disease or disorder in a subject in need thereof, comprising detecting the presence of inflammatory gastrointestinal disease or disorder in the subject, wherein if inflammatory gastrointestinal disease or disorder is detected, then administering the formulation of the present invention to the subject.
    Type: Application
    Filed: June 6, 2007
    Publication date: February 4, 2010
    Inventors: Satya Prakash, Aleksandra Malgorzata Urbanska
  • Patent number: 7586936
    Abstract: An Ethernet adapter is disclosed. The Ethernet adapter comprises a plurality of layers for allowing the adapter to receive and transmit packets from and to a processor. The plurality of layers include a demultiplexing mechanism to allow for partitioning of the processor. A Host Ethernet Adapter (HEA) is an integrated Ethernet adapter providing a new approach to Ethernet and TCP acceleration. A set of TCP/IP acceleration features have been introduced in a toolkit approach: Servers TCP/IP stacks use these accelerators when and as required. The interface between the server and the network interface controller has been streamlined by bypassing the PCI bus. The HEA supports network virtualization. The HEA can be shared by multiple OSs providing the essential isolation and protection without affecting its performance.
    Type: Grant
    Filed: April 1, 2005
    Date of Patent: September 8, 2009
    Assignee: International Business Machines Corporation
    Inventors: Ravi Kumar Arimilli, Claude Basso, Jean Louis Calvignac, Chih-Jen Chang, Philippe Damon, Ronald Edward Fuhs, Satya Prakash Sharma, Natarajan Vaidhyanathan, Fabrice Jean Verplanken, Colin Beaton Verrilli, Scott Michael Willenborg
  • Patent number: 7543908
    Abstract: Systems, methodologies, media, and other embodiments associated with clearing silicate based kogation from heating resistors employed in ink jet printing are described. One exemplary system embodiment includes a silicate kogation clearing logic configured to pulse the heating resistor at a high frequency and low pulse width to heat the resistor surface to a temperature below that required to form an ink bubble and thus below that required to eject a drop of ink. Heating the resistor facilitates breaking bonds between the silicate based kogation and the heating resistor.
    Type: Grant
    Filed: August 23, 2005
    Date of Patent: June 9, 2009
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Morgan G. Jones, Satya Prakash, Jeffrey D. Langford
  • Patent number: 7535678
    Abstract: A method and system for utilizing flexible members to reduce an operational disturbance between a slider and a flexure nose portion of a head gimbal assembly is disclosed. The method provides a slider coupled with a gimbal structure of the head gimbal assembly, the slider having a read/write head element with lead terminals thereon. The method further provides a flexure nose portion coupled with the gimbal structure. A gimbal window is provided in a stainless steel layer, the gimbal window located between the slider and the flexure nose portion on the gimbal structure. A flexible member is utilized at the gimbal window for coupling the slider and the gimbal structure, the flexible member for reducing an operational disturbance passed from the slider to the flexure nose portion of the gimbal structure.
    Type: Grant
    Filed: January 10, 2006
    Date of Patent: May 19, 2009
    Assignee: Hitachi Global Storage Technologies Netherlands B.V.
    Inventor: Satya Prakash Arya
  • Patent number: 7517056
    Abstract: A fluid ejection device includes a fluid chamber, a fluid restriction communicated with the fluid chamber, and a fluid channel communicated with the fluid restriction. The fluid restriction has a fluid restriction parameter defined as (2*W+2*H)*L/(H*W), wherein W is a width of the fluid restriction, H is a height of the fluid restriction, and L is a length of the fluid restriction. As such, the fluid restriction parameter is in a range of 1.5 to 5.75.
    Type: Grant
    Filed: February 13, 2006
    Date of Patent: April 14, 2009
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Elizabeth A. Fellner, James Pingel, Matthew David Giere, Satya Prakash, David W Jenkins, James A Feinn, Arun K Agarwal, Julie J Cox, Jules G Moritz, Ozgur Yildirim
  • Publication number: 20090077661
    Abstract: A method for improving the reliability of host data stored on Fibre Channel attached storage subsystems by performing end-to-end data integrity checks. When a read or write operation is initiated, an initial checksum for data in the read/write operation is generated and associated with the data, wherein the association exists through a plurality of layers of software and attached storage subsystems. The initial checksum is passed with the data in the read/write path. When a layer of software in the read/write path receives the initial checksum and data, the layer performs an integrity check of the data, which includes generating another checksum and comparing it to the initial checksum. If the checksums do not match, the read/write operation fails and the error is logged. If the checksums match, the integrity check is repeated through each layer in the read/write path to enable detecting data corruption at the point of source.
    Type: Application
    Filed: November 24, 2008
    Publication date: March 19, 2009
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: James Patrick Allen, Thomas Stanley Mathews, Ravi A. Shankar, Satya Prakash Sharma, Glenn Rowan Wightwick
  • Publication number: 20090051741
    Abstract: Embodiments include forming internal or external extended surface elements on a print-head substrate, at least in part, using a light beam.
    Type: Application
    Filed: October 29, 2008
    Publication date: February 26, 2009
    Inventors: Dustin W. Blair, Jeff Pollard, Matthew D. Giere, Satya Prakash
  • Publication number: 20090049278
    Abstract: A multiprocessor data processing system (MDPS) with a weakly-ordered architecture providing processing logic for substantially eliminating issuing sync instructions after every store instruction of a well-behaved application. Instructions of a well-behaved application are translated and executed by a weakly-ordered processor. The processing logic includes a lock address tracking utility (LATU), which provides an algorithm and a table of lock addresses, within which each lock address is stored when the lock is acquired by the weakly-ordered processor. When a store instruction is encountered in the instruction stream, the LATU compares the target address of the store instruction against the table of lock addresses. If the target address matches one of the lock addresses, indicating that the store instruction is the corresponding unlock instruction (or lock release instruction), a sync instruction is issued ahead of the store operation.
    Type: Application
    Filed: October 28, 2008
    Publication date: February 19, 2009
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: ANDREW DUNSHEA, SATYA PRAKASH SHARMA, MYSORE SATHYANARAYANA SRINIVAS
  • Patent number: 7489479
    Abstract: An electrical lead suspension (ELS) having partitioned air slots. The ELS includes a laminate. A first plurality of signal traces and a second plurality of traces are in a first formed layer of the laminate. The second plurality of traces may be signal traces or power traces. The laminate has a dielectric layer between the first formed layer and a second formed layer. A plurality of partitioned air slots is in the second formed layer of the laminate. The portion of the ELS having a plurality of partitioned air slots supporting the at least the first plurality of signal traces and the portion of the ELS having a second plurality of partitioned air slots or patterns supporting the second plurality of traces. The supporting of the first plurality of signal traces separate from the second plurality of traces reduces write-to-read cross talk and signal loss.
    Type: Grant
    Filed: January 18, 2005
    Date of Patent: February 10, 2009
    Assignee: Hitachi Global Storage Technologies Netherlands B.V.
    Inventors: Satya Prakash Arya, John Thomas Contreras, Klaas Klaassen, Nobumasa Nishiyama
  • Patent number: 7472332
    Abstract: A method for improving the reliability of host data stored on Fiber Channel attached storage subsystems by performing end-to-end data integrity checks. When a read or write operation is initiated, an initial checksum for data in the read/write operation is generated and associated with the data, wherein the association exists through a plurality of layers of software and attached storage subsystems. The initial checksum is passed with the data in the read/write path. When a layer of software in the read/write path receives the initial checksum and data, the layer performs an integrity check of the data, which includes generating another checksum and comparing it to the initial checksum. If the checksums do not match, the read/write operation fails and the error is logged. If the checksums match, the integrity check is repeated through each layer in the read/write path to enable detecting data corruption at the point of source.
    Type: Grant
    Filed: July 26, 2005
    Date of Patent: December 30, 2008
    Assignee: International Business Machines Corporation
    Inventors: James Patrick Allen, Thomas Stanley Mathews, Ravi A. Shankar, Satya Prakash Sharma, Glenn Rowan Wightwick
  • Patent number: 7454570
    Abstract: A multiprocessor data processing system (MDPS) with a weakly-ordered architecture providing processing logic for substantially eliminating issuing sync instructions after every store instruction of a well-behaved application. Instructions of a well-behaved application are translated and executed by a weakly-ordered processor. The processing logic includes a lock address tracking utility (LATU), which provides an algorithm and a table of lock addresses, within which each lock address is stored when the lock is acquired by the weakly-ordered processor. When a store instruction is encountered in the instruction stream, the LATU compares the target address of the store instruction against the table of lock addresses. If the target address matches one of the lock addresses, indicating that the store instruction is the corresponding unlock instruction (or lock release instruction), a sync instruction is issued ahead of the store operation.
    Type: Grant
    Filed: December 7, 2004
    Date of Patent: November 18, 2008
    Assignee: International Business Machines Corporation
    Inventors: Andrew Dunshea, Satya Prakash Sharma, Mysore Sathyanarayana Srinivas