Patents by Inventor Satyanarayana Nishtala
Satyanarayana Nishtala has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7219169Abstract: In one embodiment, a direct memory access (DMA) disk controller used in hardware-assisted data transfer operations includes command receiving logic to receive a data transfer command issued by a processor. The data transfer command identifies one or more locations in memory and multiple distinct regions on one or more disks accessible to the DMA disk controller. The DMA disk controller further includes data manipulation logic to transfer data between the memory locations and the distinct regions on the disks according to the data transfer command.Type: GrantFiled: September 30, 2002Date of Patent: May 15, 2007Assignee: Sun Microsystems, Inc.Inventors: Whay Sing Lee, Raghavendra Rao, Satyanarayana Nishtala
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Patent number: 7114014Abstract: Embodiments of the present invention provide methods and systems for data movement in data storage systems. For one embodiment, a physical data storage parcel containing a first type of data requiring a first type of processing and a second type of data requiring a second type of processing is created. The first type of data is transferred to a first memory address space via a direct memory access operation and the second type of data is transferred to a second memory address space via the direct memory access operation. For one embodiment, the first type of data and the second type of data are copied to physically distinct data storage mediums. In an alternative embodiment, the first type of data and the second type of data are copied to distinct data storage structures of the same device. Thus, the bulk memory access operations are performed via hardware, thereby reducing performance impact.Type: GrantFiled: June 27, 2003Date of Patent: September 26, 2006Assignee: Sun Microsystems, Inc.Inventors: Michael Yatziv, Satyanarayana Nishtala, Whay Sing Lee, Raghavendra J. Rao
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Publication number: 20050021888Abstract: Embodiments of the present invention provide methods and systems for data movement in data storage systems. For one embodiment, a physical data storage parcel containing a first type of data requiring a first type of processing and a second type of data requiring a second type of processing is created. The first type of data is transferred to a first memory address space via a direct memory access operation and the second type of data is transferred to a second memory address space via the direct memory access operation. For one embodiment, the first type of data and the second type of data are copied to physically distinct data storage mediums. In an alternative embodiment, the first type of data and the second type of data are copied to distinct data storage structures of the same device. Thus, the bulk memory access operations are performed via hardware, thereby reducing performance impact.Type: ApplicationFiled: June 27, 2003Publication date: January 27, 2005Inventors: Michael Yatziv, Satyanarayana Nishtala, Whay Lee, Raghavendra Rao
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Publication number: 20040268082Abstract: Embodiments of the invention provide a parcel-based, data-mapping scheme that allow for implementation of data integrity methods and variable size logical data blocks while the layout of the physical storage device remains unchanged. For one embodiment, the invention provides a method in which a virtual data storage parcel including a number of extended-size logical data storage blocks is created, and one or more physical data storage parcels, each including a number of standard-size logical data storage blocks, is created. The combined size of the one or more physical data storage parcels equals or exceeds the size of the virtual data storage parcel. The extended-size logical data storage blocks of the virtual data storage parcel are mapped to the standard-size logical data storage blocks of the one or more physical data storage parcels.Type: ApplicationFiled: June 27, 2003Publication date: December 30, 2004Inventors: Michael Yatziv, Satyanarayana Nishtala, Whay Sing Lee, Raghavendra J. Rao
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Patent number: 6834362Abstract: One embodiment of the present invention provides a system for detecting errors on a source-synchronous bus. The source-synchronous bus includes a plurality of data lines and a clock line. A transmitting mechanism configured to transmit data on the source-synchronous bus is coupled to the source-synchronous bus. A receiving mechanism configured to receive data from the source-synchronous bus is also coupled to the source-synchronous bus. An error detecting mechanism configured to detect errors on the source-synchronous bus is coupled to the receiving mechanism. The error detecting mechanism can detect errors on the plurality of data lines including errors that are caused by an error on the clock line.Type: GrantFiled: March 26, 2001Date of Patent: December 21, 2004Assignee: Sun Microsystems, Inc.Inventor: Satyanarayana Nishtala
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Publication number: 20040080533Abstract: A system and method for accessing rendered graphics over a computer network is described. In accordance with one or more exemplary embodiments of the invention, an application renders graphics on a server machine in response to a request from a client, takes a snapshot of the output of the rendered graphical images, compresses the rendered images, and sends them through the computer network to the client. On the client's side, the compressed, rendered snapshot images are decompressed and displayed. The rendered-graphics experience is the same as if the application were rendered on the local machine. Exemplary embodiments may be configured to use lossless compression schemes like GIF and also lossy compression schemes like JPEG and MPEG. In one exemplary embodiment, the client machine uses a web browser to view the snapshots of the rendered images after they are uncompressed by the client.Type: ApplicationFiled: October 23, 2002Publication date: April 29, 2004Applicant: SUN MICROSYSTEMS, INC.Inventors: Satyanarayana Nishtala, Peter Denyer
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Publication number: 20040064600Abstract: In one embodiment, a direct memory access (DMA) disk controller used in hardware-assisted data transfer operations includes command receiving logic to receive a data transfer command issued by a processor. The data transfer command identifies one or more locations in memory and multiple distinct regions on one or more disks accessible to the DMA disk controller. The DMA disk controller further includes data manipulation logic to transfer data between the memory locations and the distinct regions on the disks according to the data transfer command.Type: ApplicationFiled: September 30, 2002Publication date: April 1, 2004Inventors: Whay Sing Lee, Raghavendra Rao, Satyanarayana Nishtala
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Patent number: 6597665Abstract: A system for maintaining reliable packet distribution in a ring network with support for strongly ordered, nonidempotent commands. Each consumer node on the network maintains a record of the sequence of packets that have passed through that node, and the state of each of the packets at the time it passed through, including a record of the last known good packet and its sequence number. When a producer node detects an error condition in an acknowledgment for a packet, resends all packets beginning with the last known good packet. Each consumer node is able to process or reject the resent packets, including packets that may already have been processed, which it is aware of due to the packet and state records for all packets.Type: GrantFiled: February 25, 2000Date of Patent: July 22, 2003Assignee: Sun Microsystems, Inc.Inventors: William C. Van Loo, Satyanarayana Nishtala
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Patent number: 6519747Abstract: One embodiment of the present invention provides a system for defining signal timing for an integrated circuit device. The system operates by first creating a virtual timing reference plane for the integrated circuit device. A first signal line is then routed from a semiconductor die within the integrated circuit package to a first external connection of the integrated circuit package. Next, the system generates a first escape pattern for a first circuit trace on a printed circuit board from the first external connection to the virtual timing reference plane. This first escape pattern specifies a route from where the first external connection meets the printed circuit board to the virtual timing reference plane. Finally, the system establishes a first set of signal timings for a combination of the first signal line and the first circuit trace at the virtual timing reference plane.Type: GrantFiled: April 18, 2001Date of Patent: February 11, 2003Assignee: Sun Microsystems, Inc.Inventors: Satyanarayana Nishtala, Jayarama N. Shenoy, Tai-Yu Chou, Michael C. Freda
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Publication number: 20020194418Abstract: A data transfer control system for a computer system having a packet-switched data bus, for controlling the transfer of data words from a device having one bus width to a device having a different bus width. The first bus may be the master bus, and the second bus is a bus of a functional unit, such as a memory or other device, connected to the computer system and coupled to the master bus. When the second bus is smaller than the first bus, the data transfer control system accommodates this by transferring only partial words per clock cycle to the second bus, effectively delaying the transference of data to a rate that the second bus can handle. The transfer rate factor is substantially equal to the ratio of the second bus width to the first bus width.Type: ApplicationFiled: April 30, 2002Publication date: December 19, 2002Applicant: Sun Microsystems, Inc.Inventors: Satyanarayana Nishtala, William C. Van Loo, Zahir Ebrahim
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Publication number: 20020157072Abstract: One embodiment of the present invention provides a system for defining signal timing for an integrated circuit device. The system operates by first creating a virtual timing reference plane for the integrated circuit device. A first signal line is then routed from a semiconductor die within the integrated circuit package to a first external connection of the integrated circuit package. Next, the system generates a first escape pattern for a first circuit trace on a printed circuit board from the first external connection to the virtual timing reference plane. This first escape pattern specifies a route from where the first external connection meets the printed circuit board to the virtual timing reference plane. Finally, the system establishes a first set of circuit characteristics for a combination of the first signal line and the first circuit trace at the virtual timing reference plane.Type: ApplicationFiled: April 18, 2001Publication date: October 24, 2002Inventors: Satyanarayana Nishtala, Jayarama N. Shenoy, Tai-Yu Chou, Michael C. Freda
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Publication number: 20020138790Abstract: One embodiment of the present invention provides a system for facilitating error management on a point-to-point interconnect within a system. The system includes the point-to-point interconnect, a source of data transactions coupled to the point-to-point interconnect, and a destination of data transactions coupled to the point-to-point interconnect. A transmitting mechanism at the source transmits data transactions to the destination across the point-to-point interconnect. A receiving mechanism at the destination receives these data transactions from the point-to-point interconnect. The apparatus also includes a synchronizing mechanism that is configured to synchronize the source and destination. A local buffer at the source stores a copy of each data transaction that is transmitted from the source.Type: ApplicationFiled: March 26, 2001Publication date: September 26, 2002Inventor: Satyanarayana Nishtala
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Publication number: 20020138789Abstract: One embodiment of the present invention provides a system for detecting errors on a source-synchronous bus. The source-synchronous bus includes a plurality of data lines and a clock line. A transmitting mechanism configured to transmit data on the source-synchronous bus is coupled to the source-synchronous bus. A receiving mechanism configured to receive data from the source-synchronous bus is also coupled to the source-synchronous bus. An error detecting mechanism configured to detect errors on the source-synchronous bus is coupled to the receiving mechanism. The error detecting mechanism can detect errors on the plurality of data lines including errors that are caused by an error on the clock line.Type: ApplicationFiled: March 26, 2001Publication date: September 26, 2002Inventor: Satyanarayana Nishtala
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Patent number: 6381664Abstract: A data transfer control system for a computer system having a packet-switched data bus, for controlling the transfer of data words from a device having one bus width to a device having a different bus width. The first bus may be the master bus, and the second bus is a bus of a functional unit, such as a memory or other device, connected to the computer system and coupled to the master bus. When the second bus is smaller than the first bus, the data transfer control system accommodates this by transferring only partial words per clock cycle to the second bus, effectively delaying the transference of data to a rate that the second bus can handle. The transfer rate factor is substantially equal to the ratio of the second bus width to the first bus width.Type: GrantFiled: June 20, 2000Date of Patent: April 30, 2002Assignee: Sun Microsystems, Inc.Inventors: Satyanarayana Nishtala, William C. Van Loo, Zahir Ebrahim
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Patent number: 6272007Abstract: A computer system housing where a vertical printed circuit board, e.g., a riser card, is inserted into a socket on a computer system motherboard. Some internal space within the housing may allow optimization of system memory capacity through packing of additional memory modules on the riser card. The additional memory may be mounted on the riser card and may reside in the vertical space created between the riser card and the directly-mounted memory on the motherboard. The computer system housing further includes a chassis that may be partitioned into two separate sub-chassis for proper positioning of one or more cooling fans as well as to accommodate changes in computer system configurations with minimized retooling of the chassis. The cooling fans may be mounted at such locations on the chassis that allow optimization of air circulation and, hence, cooling within the housing.Type: GrantFiled: June 28, 1999Date of Patent: August 7, 2001Assignee: Sun Microsystems, Inc.Inventors: Kenneth Kitlas, Anita Patel, Satyanarayana Nishtala, Alan Lee Winick, Alan Lam, Winiie C. Leung, Kenneth A. Lown, Mohammed Tantoush
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Patent number: 6141741Abstract: A computer system with a multiplexed address bus that is shared by both system memory and by slave devices is described. The slave devices are incorporated into an existing system memory configuration by providing a bus controller to execute a two-cycle address sequence on the multiplexed address bus. The address sequence is followed by a transfer of data. A random latency can exist between the time of receiving address information and the time of receiving data corresponding to the address information. This random latency can be exploited by the system CPU for other computational purposes. The bus controller of the system executes multiple, or pipelined, data writes to the bus before an acknowledgement for the first data write is received. In this scheme, the acknowledgement for the first data write is typically sent during the same time period that the subsequent data writes are being received. Consequently, data transfer acknowledgements overlap data writes.Type: GrantFiled: August 29, 1996Date of Patent: October 31, 2000Assignee: Sun Microsystems, Inc.Inventors: Curtis Priem, Satyanarayana Nishtala, Michael G. Lavelle, Thomas Webber, Daniel E. Lenoski, Peter A. Mehring, Guy Moffat, Christopher R. Owen
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Patent number: 6101565Abstract: A data transfer control system for a computer system having a packet-switched data bus, for controlling the transfer of data words from a device having one bus width to a device having a different bus width. The first bus may be the master bus, and the second bus is a bus of a functional unit, such as a memory or other device, connected to the computer system and coupled to the master bus. When the second bus is smaller than the first bus, the data transfer control system accommodates this by transferring only partial words per clock cycle to the second bus, effectively delaying the transference of data to a rate that the second bus can handle. The transfer rate factor is substantially equal to the ratio of the second bus width to the first bus width.Type: GrantFiled: August 18, 1997Date of Patent: August 8, 2000Assignee: Sun Microsystems, Inc.Inventors: Satyanarayana Nishtala, William C. Van Loo, Zahir Ebrahim
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Patent number: 6064672Abstract: A system for maintaining reliable packet distribution in a ring network with support for strongly ordered, nonidempotent commands. Each consumer node on the network maintains a record of the sequence of packets that have passed through that node, and the state of each of the packets at the time it passed through, including a record of the last known good packet and its sequence number. When a producer node detects an error condition in an acknowledgment for a packet, resends all packets beginning with the last known good packet. Each consumer node is able to process or reject the resent packets, including packets that may already have been processed, which it is aware of due to the packet and state records for all packets.Type: GrantFiled: July 1, 1996Date of Patent: May 16, 2000Assignee: Sun Microsystems, Inc.Inventors: William C. Van Loo, Satyanarayana Nishtala
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Patent number: 5987579Abstract: In a computer system including a packet-switched bus, a method for requesting transactions such that memory accesses are initiated quickly. A master transmits a first portion of a transaction request packet having multiple portion. A memory controller receives the first portion of the transaction request, which includes a row address portion of a memory address. The memory controller initiates a memory access by applying a row address strobe signal to the row of the memory location in response to receiving the first portion of the request packet, and the master transmits any remaining portion of the transaction request. After the full memory address has been received, it is determined whether data stored at the memory location is to be read from a source other than the memory location. The memory controller aborts the memory access by inhibiting assertion of a column access strobe signal to the memory location if the data is to be read from a source other than the memory location.Type: GrantFiled: March 27, 1997Date of Patent: November 16, 1999Assignee: Sun Microsystems, Inc.Inventors: Satyanarayana Nishtala, Zahir Ebrahim, William C. Van Loo, Raymond Ng, Louis F. Coffin, III
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Patent number: 5919265Abstract: A system clock generator for a computer system to efficiently transfer data from a source subsystem to a destination subsystem of the computer system. The system clock generator generates a globally synchronized clock signal for the source subsystem and the destination subsystem. The source subsystem includes a clock generator for generating a source clk (SRC.sub.-- CLK) signal and a source-synchronous clock (SRC.sub.-- SYN.sub.-- CLK) signal for the source subsystem and destination subsystem, respectively. The SRC.sub.-- SYN.sub.-- CLK signal is generated whenever data is transferred from the source subsystem to the destination subsystem. Upon receiving the data and SRC.sub.-- SYN.sub.-- CLK signal from the source subsystem, the data is synchronized at the destination subsystem using the SRC.sub.-- SYN.sub.-- CLK signal. Since the source and destination subsystems are synchronized by the system clock signal, an incoming data stream can be synchronized within one system clock cycle.Type: GrantFiled: May 28, 1996Date of Patent: July 6, 1999Assignee: Sun Microsystems, Inc.Inventors: Satyanarayana Nishtala, William Van Loo