Patents by Inventor Satyanarayana V Nitta
Satyanarayana V Nitta has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9018767Abstract: A dielectric stack and method of depositing the stack to a substrate using a single step deposition process. The dielectric stack includes a dense layer and a porous layer of the same elemental compound with different compositional atomic percentage, density, and porosity. The stack enhances mechanical modulus strength and enhances oxidation and copper diffusion barrier properties. The dielectric stack has inorganic or hybrid inorganic-organic random three-dimensional covalent bonding throughout the network, which contain different regions of different chemical compositions such as a cap component adjacent to a low-k component of the same type of material but with higher porosity.Type: GrantFiled: May 23, 2014Date of Patent: April 28, 2015Assignee: International Business Machines CorporationInventors: Griselda Bonilla, Alfred Grill, Thomas J. Haigh, Jr., Satyanarayana V. Nitta, Son Nguyen
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Patent number: 8952539Abstract: Methods for producing air gap-containing metal-insulator interconnect structures for VLSI and ULSI devices using a photo-patternable low k material as well as the air gap-containing interconnect structure that is formed are disclosed. More particularly, the methods described herein provide interconnect structures built in a photo-patternable low k material in which air gaps are defined by photolithography in the photo-patternable low k material. In the methods of the present invention, no etch step is required to form the air gaps. Since no etch step is required in forming the air gaps within the photo-patternable low k material, the methods disclosed in this invention provide highly reliable interconnect structures.Type: GrantFiled: January 16, 2014Date of Patent: February 10, 2015Assignee: International Business Machines CorporationInventors: Lawrence A. Clevenger, Maxime Darnon, Satyanarayana V. Nitta, Anthony D. Lisi, Qinghuang Lin
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Patent number: 8896120Abstract: Methods for producing air gap-containing metal-insulator interconnect structures for VLSI and ULSI devices using a photo-patternable low k material as well as the air gap-containing interconnect structure that is formed are disclosed. More particularly, the methods described herein provide interconnect structures built in a photo-patternable low k material in which air gaps of different depths are defined by photolithography in the photo-patternable low k material. In the methods of the present invention, no etch step is required to form the air gaps. Since no etch step is required in forming the air gaps within the photo-patternable low k material, the methods disclosed in this invention provide highly reliable interconnect structures.Type: GrantFiled: April 27, 2010Date of Patent: November 25, 2014Assignee: International Business Machines CorporationInventors: Lawrence A. Clevenger, Maxime Darnon, Qinghuang Lin, Anthony D. Lisi, Satyanarayana V. Nitta
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Publication number: 20140284815Abstract: A dielectric stack and method of depositing the stack to a substrate using a single step deposition process. The dielectric stack includes a dense layer and a porous layer of the same elemental compound with different compositional atomic percentage, density, and porosity. The stack enhances mechanical modulus strength and enhances oxidation and copper diffusion barrier properties. The dielectric stack has inorganic or hybrid inorganic-organic random three-dimensional covalent bonding throughout the network, which contain different regions of different chemical compositions such as a cap component adjacent to a low-k component of the same type of material but with higher porosity.Type: ApplicationFiled: May 23, 2014Publication date: September 25, 2014Applicant: International Business Machines CorporationInventors: Griselda Bonilla, Alfred Grill, Thomas J. Haigh, JR., Satyanarayana V. Nitta, Son Nguyen
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Publication number: 20140256154Abstract: A dielectric stack and method of depositing the stack to a substrate using a single step deposition process. The dielectric stack includes a dense layer and a porous layer of the same elemental compound with different compositional atomic percentage, density, and porosity. The stack enhances mechanical modulus strength and enhances oxidation and copper diffusion barrier properties. The dielectric stack has inorganic or hybrid inorganic-organic random three-dimensional covalent bonding throughout the network, which contain different regions of different chemical compositions such as a cap component adjacent to a low-k component of the same type of material but with higher porosity.Type: ApplicationFiled: May 23, 2014Publication date: September 11, 2014Applicant: International Business Machines CorporationInventors: Griselda Bonilla, Alfred Grill, Thomas J. Haigh, JR., Satyanarayana V. Nitta, Son Nguyen
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Patent number: 8809183Abstract: A selective conductive cap is deposited on exposed metal surfaces of a metal line by electroless plating selective to exposed underlying dielectric surfaces of a metal interconnect structure. A dielectric material layer is deposited on the selective conductive cap and the exposed underlying dielectric layer without a preclean. The dielectric material layer is planarized to form a horizontal planar surface that is coplanar with a topmost surface of the selective conductive cap. A preclean is performed and a dielectric cap layer is deposited on the selective conductive cap and the planarized surface of the dielectric material layer. Because the interface including a surface damaged by the preclean is vertically offset from the topmost surface of the metal line, electromigration of the metal in the metal line along the interface is reduced or eliminated.Type: GrantFiled: September 21, 2010Date of Patent: August 19, 2014Assignee: International Business Machines CorporationInventors: Griselda Bonilla, Lawrence A. Clevenger, Elbert E. Huang, Satyanarayana V. Nitta, Shom Ponoth
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Patent number: 8779600Abstract: A dielectric stack and method of depositing the stack to a substrate using a single step deposition process. The dielectric stack includes a dense layer and a porous layer of the same elemental compound with different compositional atomic percentage, density, and porosity. The stack enhances mechanical modulus strength and enhances oxidation and copper diffusion barrier properties. The dielectric stack has inorganic or hybrid inorganic-organic random three-dimensional covalent bonding throughout the network, which contain different regions of different chemical compositions such as a cap component adjacent to a low-k component of the same type of material but with higher porosity.Type: GrantFiled: January 5, 2012Date of Patent: July 15, 2014Assignee: International Business Machines CorporationInventors: Son Van Nguyen, Griselda Bonilla, Alfred Grill, Thomas J. Haigh, Jr., Satyanarayana V. Nitta
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Publication number: 20140131880Abstract: Methods for producing air gap-containing metal-insulator interconnect structures for VLSI and ULSI devices using a photo-patternable low k material as well as the air gap-containing interconnect structure that is formed are disclosed. More particularly, the methods described herein provide interconnect structures built in a photo-patternable low k material in which air gaps are defined by photolithography in the photo-patternable low k material. In the methods of the present invention, no etch step is required to form the air gaps. Since no etch step is required in forming the air gaps within the photo-patternable low k material, the methods disclosed in this invention provide highly reliable interconnect structures.Type: ApplicationFiled: January 16, 2014Publication date: May 15, 2014Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Lawrence A. Clevenger, Maxime Darnon, Satyanarayana V. Nitta, Anthony D. Lisi, Qinghuang Lin
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Publication number: 20140117457Abstract: An integrated circuit and method includes a substrate, a plurality of semiconductor device layers monolithically integrated on the substrate, and a metal wiring layer with vias interconnecting the plurality of semiconductor device layers. The semiconductor device layers are devoid of bonding or joining interface with the substrate.Type: ApplicationFiled: January 6, 2014Publication date: May 1, 2014Applicant: International Business Machines CorporationInventors: Stephen M. Gates, Daniel C. Edelstein, Satyanarayana V. Nitta
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Publication number: 20140120667Abstract: A method of fabricating a monolithic integrated circuit using a single substrate, the method including forming a first semiconductor layer from a substrate, fabricating semiconductor devices on the substrate, fabricating at least one metal wiring layer on the semiconductor devices, forming at least one dielectric layer in integral contact with the at least one metal wiring layer, forming contact openings through the at least one dielectric layer to expose regions of the at least one metal wiring layer, integrally forming, from the substrate, a second semiconductor layer on the dielectric layer, and in contact with the at least one metal wiring layer through the contact openings, and forming a plurality of non-linear semiconductor devices in said second semiconductor layer.Type: ApplicationFiled: January 6, 2014Publication date: May 1, 2014Applicant: International Business Machines CorporationInventors: Stephen M Gates, Daniel C. Edelstein, Satyanarayana V. Nitta
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Patent number: 8642252Abstract: Methods for producing air gap-containing metal-insulator interconnect structures for VLSI and ULSI devices using a photo-patternable low k material as well as the air gap-containing interconnect structure that is formed are disclosed. More particularly, the methods described herein provide interconnect structures built in a photo-patternable low k material in which air gaps are defined by photolithography in the photo-patternable low k material. In the methods of the present invention, no etch step is required to form the air gaps. Since no etch step is required in forming the air gaps within the photo-patternable low k material, the methods disclosed in this invention provide highly reliable interconnect structures.Type: GrantFiled: March 10, 2010Date of Patent: February 4, 2014Assignee: International Business Machines CorporationInventors: Lawrence A. Clevenger, Maxime Darnon, Satyanarayana V. Nitta, Anthony D. Lisi, Qinghuang Lin
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Patent number: 8629561Abstract: Methods for producing air gap-containing metal-insulator interconnect structures for VLSI and ULSI devices using a photo-patternable low k material as well as the air gap-containing interconnect structure that is formed are disclosed. More particularly, the methods described herein provide interconnect structures built in a photo-patternable low k material in which air gaps are defined by photolithography in the photo-patternable low k material. In the methods of the present invention, no etch step is required to form the air gaps. Since no etch step is required in forming the air gaps within the photo-patternable low k material, the methods disclosed in this invention provide highly reliable interconnect structures.Type: GrantFiled: July 3, 2012Date of Patent: January 14, 2014Assignee: International Business Machines CorporationInventors: Lawrence A. Clevenger, Maxime Darnon, Qinghuang Lin, Anthony D. Lisi, Satyanarayana V. Nitta
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Patent number: 8624323Abstract: A monolithic integrated circuit and method includes a substrate, a plurality of semiconductor device layers monolithically integrated on the substrate, and a metal wiring layer with vias interconnecting the plurality of semiconductor device layers. The semiconductor device layers are devoid of bonding or joining interface with the substrate.Type: GrantFiled: May 31, 2011Date of Patent: January 7, 2014Assignee: International Business Machines CorporationInventors: Stephen M. Gates, Daniel C. Edelstein, Satyanarayana V. Nitta
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Publication number: 20130234260Abstract: The present disclosure provides a method of forming an interconnect to an electrical device. In one embodiment, the method of forming an interconnect includes providing a device layer on a substrate, wherein the device layer comprises at least one electrical device, an intralevel dielectric over the at least one electrical device, and a contact that is in electrical communication with the at least one electrical device. An interconnect metal layer is formed on the device layer, and a tantalum-containing etch mask is formed on a portion of the interconnect metal layer. The interconnect metal layer is etched to provide a trapezoid shaped interconnect in communication with the at least one electrical device. The trapezoid shaped interconnect has a first surface that is in contact with the device layer with a greater width than a second surface of the trapezoid shaped interconnect that is in contact with the tantalum-containing etch mask.Type: ApplicationFiled: April 26, 2013Publication date: September 12, 2013Applicant: International Business Machines CorporationInventors: Cyril Cabral, Jr., Sebastian U. Engelmann, Benjamin Fletcher, Eric A. Joseph, Satyanarayana V. Nitta
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Patent number: 8525169Abstract: The present disclosure relates to a secure device having a physical unclonable function. The device includes an integrated circuit having a semiconducting material in at least one via in a backend of the integrated circuit. The present disclosure also relates to a method for manufacturing a secure device having a physical unclonable function. The method includes providing an integrated circuit and adding a semiconducting material to at least one via in a backend of the integrated circuit. In some instances a property of the semiconducting material in the at least one via is measured to derive a signature.Type: GrantFiled: August 10, 2012Date of Patent: September 3, 2013Assignee: International Business Machines CorporationInventors: Daniel C. Edelstein, Stephen M. Gates, Edward W. Kiewra, Satyanarayana V. Nitta, Ramachandran Muralidhar, Dirk Pfeiffer
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Patent number: 8491987Abstract: A method for forming a self aligned pattern on an existing pattern on a substrate comprising applying a coating of a solution containing a masking material in a carrier, the masking material having an affinity for portions of the existing pattern; and allowing at least a portion of the masking material to preferentially assemble to the portions of the existing pattern. The pattern may be comprised of a first set of regions of the substrate having a first atomic composition and a second set of regions of the substrate having a second atomic composition different from the first composition. The first set of regions may include one or more metal elements and the second set of regions may include a dielectric. The first and second regions may be treated to have different surface properties. Structures made in accordance with the method. Compositions useful for practicing the method.Type: GrantFiled: June 30, 2008Date of Patent: July 23, 2013Assignee: International Business Machines CorporationInventors: Matthew E Colburn, Stephen M Gates, Jeffrey C Hedrick, Elbert Huang, Satyanarayana V Nitta, Sampath Purushothaman, Muthumanickam Sankarapandian
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Publication number: 20130175697Abstract: A dielectric stack and method of depositing the stack to a substrate using a single step deposition process. The dielectric stack includes a dense layer and a porous layer of the same elemental compound with different compositional atomic percentage, density, and porosity. The stack enhances mechanical modulus strength and enhances oxidation and copper diffusion barrier properties. The dielectric stack has inorganic or hybrid inorganic-organic random three-dimensional covalent bonding throughout the network, which contain different regions of different chemical compositions such as a cap component adjacent to a low-k component of the same type of material but with higher porosity.Type: ApplicationFiled: January 5, 2012Publication date: July 11, 2013Applicant: International Business Machines CorporationInventors: Son Van Nguyen, Griselda Bonilla, Alfred Grill, Thomas J. Haigh, JR., Satyanarayana V. Nitta
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Patent number: 8440505Abstract: An integrated circuit including an active region a passive region and a cut line in the passive region includes a passivation layer that includes an outer nitride layer over an oxide layer. The integrated circuit also includes a crack stop below the passivation layer and in the passive region, and a solder ball in the active region. The passivation layer has a trench formed therein in a location that is further from the active region than the crack stop and closer to the active region than the cut line, the trench passing completely through the outer nitride layer and a least a portion of the way through the oxide layer.Type: GrantFiled: January 28, 2010Date of Patent: May 14, 2013Assignee: International Business Machines CorporationInventors: Deepak Kulkarni, Michael W. Lane, Satyanarayana V. Nitta, Shom Ponoth
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Patent number: 8431486Abstract: The present disclosure provides a method of forming an interconnect to an electrical device. In one embodiment, the method of forming an interconnect includes providing a device layer on a substrate, wherein the device layer comprises at least one electrical device, an intralevel dielectric over the at least one electrical device, and a contact that is in electrical communication with the at least one electrical device. An interconnect metal layer is formed on the device layer, and a tantalum-containing etch mask is formed on a portion of the interconnect metal layer. The interconnect metal layer is etched to provide a trapezoid shaped interconnect in communication with the at least one electrical device. The trapezoid shaped interconnect has a first surface that is in contact with the device layer with a greater width than a second surface of the trapezoid shaped interconnect that is in contact with the tantalum-containing etch mask.Type: GrantFiled: August 10, 2010Date of Patent: April 30, 2013Assignee: International Business Machines CorporationInventors: Cyril Cabral, Jr., Sebastian U. Engelmann, Benjamin Fletcher, Eric A. Joseph, Satyanarayana V. Nitta
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Patent number: 8421239Abstract: A method for forming crenulated conductors and a device having crenulated conductors includes forming a hardmask layer on a dielectric layer, and patterning the hardmask layer. Trenches are etched in the dielectric layer using the hardmask layer such that the trenches have shallower portions and deeper portions alternating along a length of the trench. A conductor is deposited in the trenches such that crenulated conductive lines are formed having different depths periodically disposed along the length of the conductive line.Type: GrantFiled: March 16, 2010Date of Patent: April 16, 2013Assignee: International Business Machines CorporationInventors: Griselda Bonilla, Elbert E. Huang, Satyanarayana V. Nitta, Shom Ponoth