Abstract: A microelectronic structure and a method for fabricating the microelectronic structure provide a plurality of voids interposed between a plurality of conductor layers. The plurality of voids is also located between a liner layer and an inter-level dielectric layer. The voids provide for enhanced electrical performance of the microelectronic structure.

Abstract: Methods for producing air gap-containing metal-insulator interconnect structures for VLSI and ULSI devices using a photo-patternable low k material as well as the air gap-containing interconnect structure that is formed are disclosed. More particularly, the methods described herein provide interconnect structures built in a photo-patternable low k material in which air gaps of different depths are defined by photolithography in the photo-patternable low k material. In the methods of the present invention, no etch step is required to form the air gaps. Since no etch step is required in forming the air gaps within the photo-patternable low k material, the methods disclosed in this invention provide highly reliable interconnect structures.

Abstract: A method for forming crenulated conductors and a device having crenulated conductors includes forming a hardmask layer on a dielectric layer, and patterning the hardmask layer. Trenches are etched in the dielectric layer using the hardmask layer such that the trenches have shallower portions and deeper portions alternating along a length of the trench. A conductor is deposited in the trenches such that crenulated conductive lines are formed having different depths periodically disposed along the length of the conductive line.

Abstract: Methods for producing air gap-containing metal-insulator interconnect structures for VLSI and ULSI devices using a photo-patternable low k material as well as the air gap-containing interconnect structure that is formed are disclosed. More particularly, the methods described herein provide interconnect structures built in a photo-patternable low k material in which air gaps are defined by photolithography in the photo-patternable low k material. In the methods of the present invention, no etch step is required to form the air gaps. Since no etch step is required in forming the air gaps within the photo-patternable low k material, the methods disclosed in this invention provide highly reliable interconnect structures.

Abstract: A hard mask is formed on an interconnect structure comprising a low-k material layer and a metal feature embedded therein. A block polymer is applied to the hard mask layer, self-assembled, and patterned to form a polymeric matrix of a polymeric block component and containing cylindrical holes. The hard mask and the low-k material layer therebelow are etched to form cavities. A conductive material is plated on exposed metallic surfaces including portions of top surfaces of the metal feature to form metal pads. Metal silicide pads are formed by exposure of the metal pads to a silicon containing gas. An etch is performed to enlarge and merge the cavities in the low-k material layer. The metal feature is protected from the etch by the metal silicide pads. An interconnect structure having an air gap and free of defects to surfaces of the metal feature is formed.

Abstract: A method of selectively altering material properties of a substrate in one region while making a different alteration of material properties in an adjoining region is provided. The method includes selectively masking a first portion of the substrate during a first exposure and selectively masking a second portion of the substrate during a second exposure. Additionally, a mask may be formed having more than one thickness where each thickness will selectively reduce the amount of energy from a blanket exposure of the substrate thereby allowing a substrate to receive different levels of energy dosage in a single blanket exposure.

Abstract: Methods for fabricating a hybrid interconnect structure that possesses a higher interconnect capacitance in one set of regions than in other regions on the same microelectronic chip. Several methods to fabricate such a structure are provided. Circuit implementations of such hybrid interconnect structures are described that enable increased static noise margin and reduce the leakage in SRAM cells and common power supply voltages for SRAM and logic in such a chip. Methods that enable combining these circuit benefits with higher interconnect performance speed and superior mechanical robustness in such chips are also taught.

Abstract: A method for forming a self aligned pattern on an existing pattern on a substrate comprising applying a coating of a solution containing a masking material in a carrier, the masking material having an affinity for portions of the existing pattern; and allowing at least a portion of the masking material to preferentially assemble to the portions of the existing pattern. The pattern may be comprised of a first set of regions of the substrate having a first atomic composition and a second set of regions of the substrate having a second atomic composition different from the first composition. The first set of regions may include one or more metal elements and the second set of regions may include a dielectric. The first and second regions may be treated to have different surface properties. Structures made in accordance with the method. Compositions useful for practicing the method.

Abstract: Sub-lithographic dimensioned air gap formation and related structure are disclosed. In one embodiment, a method includes forming a dielectric layer including interconnects on a substrate; depositing a cap layer on the dielectric layer; depositing a photoresist over the cap layer; patterning the photoresist to include a first trench pattern at most partially overlying the interconnects; forming a spacer within the first trench pattern to form a second trench pattern having a sub-lithographic dimension; transferring the second trench pattern into the cap layer and into the dielectric layer between the interconnects; and depositing another dielectric layer to form an air gap by pinching off the trench in the dielectric layer.

Abstract: Method of manufacturing a structure which includes the steps of providing a structure having an insulator layer with at least one interconnect, forming a sub lithographic template mask over the insulator layer, and selectively etching the insulator layer through the sub lithographic template mask to form sub lithographic features spanning to a sidewall of the plurality of interconnects.

Abstract: A process to produce an airgap on a substrate having a dielectric layer comprises defining lines by lithography where airgaps are required. The lines' dimensions are shrunk by a trimming process (isotropic etching). The tone of the patterns is reversed by applying a planarizing layer which is etched down to the top of the patterns. The photoresist is removed, leading to sub-lithographic trenches which are transferred into a cap layer and eventually into the dielectric between two metal lines. The exposed dielectric is eventually damaged, and is etched out, leading to airgaps between metal lines. The gap is sealed by the pinch-off occurring during the deposition of the subsequent dielectric.

Abstract: A metal interconnect structure includes at least a pair of metal lines, a cavity therebetween, and a dielectric metal-diffusion barrier layer located on at least one portion of walls of the cavity. After formation of a cavity between the pair of metal lines, the dielectric metal-diffusion barrier layer is formed on the exposed surfaces of the cavity. A dielectric material layer is formed above the pair of metal lines to encapsulate the cavity. The dielectric metal-diffusion barrier layer prevents diffusion of metal and impurities from one metal line to another metal line and vice versa, thereby preventing electrical shorts between the pair of metal lines.

Abstract: A hard mask is formed on an interconnect structure comprising a low-k material layer and a metal feature embedded therein. A block polymer is applied to the hard mask layer, self-assembled, and patterned to form a polymeric matrix of a polymeric block component and containing cylindrical holes. The hard mask and the low-k material layer therebelow are etched to form cavities. A conductive material is plated on exposed metallic surfaces including portions of top surfaces of the metal feature to form metal pads. Metal silicide pads are formed by exposure of the metal pads to a silicon containing gas. An etch is performed to enlarge and merge the cavities in the low-k material layer. The metal feature is protected from the etch by the metal silicide pads. An interconnect structure having an air gap and free of defects to surfaces of the metal feature is formed.

Abstract: Method of manufacturing a structure which includes the steps of providing a structure having an insulator layer with at least one interconnect, forming a sub lithographic template mask over the insulator layer, and selectively etching the insulator layer through the sub lithographic template mask to form sub lithographic features spanning to a sidewall of the at least one interconnect.

Abstract: A hard mask is formed on an interconnect structure comprising a low-k material layer and a metal feature embedded therein. A block polymer is applied to the hard mask layer, self-assembled, and patterned to form a polymeric matrix of a polymeric block component and containing cylindrical holes. The hard mask and the low-k material layer therebelow are etched to form cavities. A conductive material is plated on exposed metallic surfaces including portions of top surfaces of the metal feature to form metal pads. Metal silicide pads are formed by exposure of the metal pads to a silicon containing gas. An etch is performed to enlarge and merge the cavities in the low-k material layer. The metal feature is protected from the etch by the metal silicide pads. An interconnect structure having an air gap and free of defects to surfaces of the metal feature is formed.

Abstract: Often used to reduce the RC delay in integrated circuits are dielectric films of porous organosilicates which have a silica like backbone with alkyl or aryl groups (to add hydrophobicity to the materials and create free volume) attached directly to the Si atoms in the network. Si—R bonds rarely survive an exposure to plasmas or chemical treatments commonly used in processing; this is especially the case in materials with an open cell pore structure. When Si—R bonds are broken, the materials lose hydrophobicity, due to formation of hydrophilic silanols and low dielectric constant is compromised. A method by which the hydrophobicity of the materials is recovered using a novel class of silylation agents which may have the general formula (R2N)XSiR?Y where X and Y are integers from 1 to 3 and 3 to 1 respectively, and where R and R? are selected from the group of hydrogen, alkyl, aryl, allyl and a vinyl moiety. Mechanical strength of porous organosilicates is also improved as a result of the silylation treatment.

Abstract: A method of restoring the dielectric constant, loss and leakage of an exposed surface of a low k dielectric material caused during dry etching of the low k dielectric material prior to the removal of the damaged layer by wet etch chemistries is provided. Once restored, the surface of the dielectric material will no longer be susceptible to removal by the highly anisotropic wet etching process. However, the wet etch will still pose an advantage as it can remove any etch/ash residues at the bottom of a feature formed into the low k dielectric material.

Abstract: Deep trenches formed beneath contact level in a semiconductor substrate function as crackstops, in a die area or in a scribe area of the wafer, and may be disposed in rows of increasing distance from a device which they are intended to protect, and may be located under a lattice work crackstop structure in an interconnect stack layer. The deep trenches may remain unfilled, or may be filled with a dielectric material or conductor. The deep trenches may have a depth into the substrate of approximately 1 micron to 100 microns, and a width of approximately 10 nm to 10 microns.

Abstract: An integrated circuit including an active region a passive region and a cut line in the passive region includes a passivation layer that includes an outer nitride layer over an oxide layer. The integrated circuit also includes a crack stop below the passivation layer and in the passive region, and a solder ball in the active region. The passivation layer has a trench formed therein in a location that is further from the active region than the crack stop and closer to the active region than the cut line, the trench passing completely through the outer nitride layer and a least a portion of the way through the oxide layer.

Abstract: An interconnect in provided which comprises a copper conductor having both a top surface and a lower surface, with caps formed on the top surface of the metallic conductor. The cap is formed of dual laminations or multiple laminations of films with the laminated films including an Ultra-Violet (UV) blocking film and a diffusion barrier film. The diffusion barrier film and the UV blocking film may be separated by an intermediate film.