Patents by Inventor Satyendra Singh
Satyendra Singh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10892405Abstract: A Hall-effect sensor package includes and an IC die including a Hall-Effect element and a leadframe including leads on a first side providing a first field generating current (FGC) path including ?1 first FGC input pin coupled by a reduced width first curved head over or under the Hall-effect sensor element to ?1 first FGC output pin, and second leads on a second side of the package. Some leads on the second side are attached to bond pads on the IC die including the output of the Hall-effect element. A clip is attached at one end to the first FGC input pin and at another end to a location on the first FGC output pin, having a reduced width second curved head in between that is over or under the Hall-effect sensor element opposite the first head.Type: GrantFiled: May 7, 2019Date of Patent: January 12, 2021Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Ming Li, Yiqi Tang, Jie Chen, Enis Tuncer, Usman Mahmood Chaudhry, Tony Ray Larson, Rajen Manicon Murugan, John Paul Tellkamp, Satyendra Singh Chauhan
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Publication number: 20200357987Abstract: A Hall-effect sensor package includes and an IC die including a Hall-Effect element and a leadframe including leads on a first side providing a first field generating current (FGC) path including ?1 first FGC input pin coupled by a reduced width first curved head over or under the Hall-effect sensor element to ?1 first FGC output pin, and second leads on a second side of the package. Some leads on the second side are attached to bond pads on the IC die including the output of the Hall-effect element. A clip is attached at one end to the first FGC input pin and at another end to a location on the first FGC output pin, having a reduced width second curved head in between that is over or under the Hall-effect sensor element opposite the first head.Type: ApplicationFiled: May 7, 2019Publication date: November 12, 2020Inventors: Ming Li, Yiqi Tang, Jie Chen, Enis Tuncer, Usman Mahmood Chaudhry, Tony Ray Larson, Rajen Manicon Murugan, John Paul Tellkamp, Satyendra Singh Chauhan
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Publication number: 20190088628Abstract: A Multi-Chip Module (MCM) package includes a substrate having a plurality of metal terminals and at least a first die attach area. An encapsulant is around the substrate including on at least a portion of the topside and at least a portion of the bottomside of the package. At least a first device including at least two device terminals is attached face up on the first die attach area. At least a second device including at least two device terminals is flip-chip attached and stacked on the first device. At least one of the first device and second device include a transistor. At least one metal clip is between the first device and second device including a plurality of clip portions isolated from one another connecting at least one device terminal of each of the first device and second device to respective metal terminals of the plurality of metal terminals.Type: ApplicationFiled: November 8, 2018Publication date: March 21, 2019Inventors: Marie Denison, Richard Saye, Takahiko Kudoh, Satyendra Singh Chauhan
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Patent number: 10128219Abstract: A Multi-Chip Module (MCM) package includes a substrate having a plurality of metal terminals and at least a first die attach area. An encapsulant is around the substrate including on at least a portion of the topside and at least a portion of the bottomside of the package. At least a first device including at least two device terminals is attached face up on the first die attach area. At least a second device including at least two device terminals is flip-chip attached and stacked on the first device. At least one of the first device and second device include a transistor. At least one metal clip is between the first device and second device including a plurality of clip portions isolated from one another connecting at least one device terminal of each of the first device and second device to respective metal terminals of the plurality of metal terminals.Type: GrantFiled: April 25, 2013Date of Patent: November 13, 2018Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Marie Denison, Richard Saye, Takahiko Kudoh, Satyendra Singh Chauhan
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Patent number: 9268811Abstract: A system and method for replaying writes in a replication log is provided. The replay of writes in the replication log can begin at some point after detecting an imminent overflow condition is detected. One method involves detecting the imminent overflow condition, performing a first synchronization for regions of the first volume based upon information in a first subset of the replication log, processing information in a second subset of the replication log while the first synchronization is ongoing, and performing a second synchronization for regions of the first volume based upon information in the second subset of the replication log, subsequent to the first synchronization and subsequent to processing the information in the second subset of the replication log.Type: GrantFiled: October 25, 2010Date of Patent: February 23, 2016Assignee: Symantec CorporationInventor: Satyendra Singh Thakur
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Publication number: 20130285260Abstract: A Multi-Chip Module (MCM) package includes a substrate having a plurality of metal terminals and at least a first die attach area. An encapsulant is around the substrate including on at least a portion of the topside and at least a portion of the bottomside of the package. At least a first device including at least two device terminals is attached face up on the first die attach area. At least a second device including at least two device terminals is flip-chip attached and stacked on the first device. At least one of the first device and second device include a transistor. At least one metal clip is between the first device and second device including a plurality of clip portions isolated from one another connecting at least one device terminal of each of the first device and second device to respective metal terminals of the plurality of metal terminals.Type: ApplicationFiled: April 25, 2013Publication date: October 31, 2013Applicant: Texas Instruments IncorporatedInventors: MARIE DENISON, RICHARD SAYE, TAKAHIKO KUDOH, SATYENDRA SINGH CHAUHAN
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Patent number: 8193093Abstract: A die to die bonding system and method includes an upper die having a front side, a back side, and a fully filled thru silicon via, a portion of the fully filled thru silicon via protruding from the back side of the upper die. A lower die includes a front side, a back side, and a partially filled thru silicon via formed to define a via opening exposed to the front side of the die, a portion of the partially filled thru silicon via protruding from the back side of the lower die. An interconnect bonds an outer surface of the protruding portion of the upper die thru silicon via with an inner surface of via opening in the lower die.Type: GrantFiled: May 18, 2011Date of Patent: June 5, 2012Assignee: Texas Instruments IncorporatedInventor: Satyendra Singh Chauhan
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Patent number: 8039309Abstract: A method of making integrated circuit packages using a conductive plate as a substrate includes forming a partial circuit pattern on one side of the conductive plate by stamping or selectively removing a portion of the conductive plate through part of its thickness, and then electrically coupling semiconductor dies to the formed patterns on the conductive plate. The method further includes encapsulating at least a portion of the dies and the conductive plate with an encapsulant and removing a portion of the conductive plate from the side opposite the patterned side to form conductive traces based on the formed pattern.Type: GrantFiled: May 7, 2008Date of Patent: October 18, 2011Assignee: Texas Instruments IncorporatedInventors: Masood Murtuza, Satyendra Singh Chauhan, Donald C. Abbott
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Publication number: 20110250720Abstract: A die to die bonding system and method includes an upper die having a front side, a back side, and a fully filled thru silicon via, a portion of the fully filled thru silicon via protruding from the back side of the upper die. A lower die includes a front side, a back side, and a partially filled thru silicon via formed to define a via opening exposed to the front side of the die, a portion of the partially filled thru silicon via protruding from the back side of the lower die. An interconnect bonds an outer surface of the protruding portion of the upper die thru silicon via with an inner surface of via opening in the lower die.Type: ApplicationFiled: May 18, 2011Publication date: October 13, 2011Applicant: TEXAS INSTRUMENTS INCORPORATEDInventor: Satyendra Singh CHAUHAN
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Patent number: 8017439Abstract: A method of forming stacked electronic articles using a through substrate via (TSV) wafer includes mounting a first carrier wafer to a top side of the TSV wafer using a first adhesive material that has a first debonding temperature. The TSV wafer is thinned from a bottom side of the TSV wafer to form a thinned TSV wafer. A second carrier wafer is mounted to the bottom side of the TSV wafer using a second adhesive material that has a second debonding temperature that is higher as compared to the first debonding temperature. The thinned TSV wafer is heated to a temperature above the first debonding temperature to remove the first carrier wafer from the thinned TSV wafer. At least one singulated IC die is bonded to TSV die formed on the top surface of the thinned TSV wafer to form the stacked electronic article.Type: GrantFiled: January 26, 2010Date of Patent: September 13, 2011Assignee: Texas Instruments IncorporatedInventors: Yoshimi Takahashi, Masood Murtuza, Rajiv Dunne, Satyendra Singh Chauhan
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Publication number: 20110183464Abstract: A method of forming stacked electronic articles using a through substrate via (TSV) wafer includes mounting a first carrier wafer to a top side of the TSV wafer using a first adhesive material that has a first debonding temperature. The TSV wafer is thinned from a bottom side of the TSV wafer to form a thinned TSV wafer. A second carrier wafer is mounted to the bottom side of the TSV wafer using a second adhesive material that has a second debonding temperature that is higher as compared to the first debonding temperature. The thinned TSV wafer is heated to a temperature above the first debonding temperature to remove the first carrier wafer from the thinned TSV wafer. At least one singulated IC die is bonded to TSV die formed on the top surface of the thinned TSV wafer to form the stacked electronic article.Type: ApplicationFiled: January 26, 2010Publication date: July 28, 2011Applicant: TEXAS INSTRUMENTS INCORPORATEDInventors: Yoshimi Takahashi, Masood Murtuza, Rajiv Dunne, Satyendra Singh Chauhan
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Patent number: 7973416Abstract: A die to die bonding system and method includes an upper die having a front side, a back side, and a fully filled thru silicon via, a portion of the fully filled thru silicon via protruding from the back side of the upper die. A lower die includes a front side, a back side, and a partially filled thru silicon via formed to define a via opening exposed to the front side of the die, a portion of the partially filled thru silicon via protruding from the back side of the lower die. An interconnect bonds an outer surface of the protruding portion of the upper die thru silicon via with an inner surface of via opening in the lower die.Type: GrantFiled: February 11, 2009Date of Patent: July 5, 2011Assignee: Texas Instruments IncorporatedInventor: Satyendra Singh Chauhan
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Publication number: 20100320575Abstract: A die to die bonding system and method includes an upper die having a front side, a back side, and a fully filled thru silicon via, a portion of the fully filled thru silicon via protruding from the back side of the upper die. A lower die includes a front side, a back side, and a partially filled thru silicon via formed to define a via opening exposed to the front side of the die, a portion of the partially filled thru silicon via protruding from the back side of the lower die. An interconnect bonds an outer surface of the protruding portion of the upper die thru silicon via with an inner surface of via opening in the lower die.Type: ApplicationFiled: February 11, 2009Publication date: December 23, 2010Inventor: Satyendra Singh CHAUHAN
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Publication number: 20100200961Abstract: A die to die bonding system and method includes an upper die having a front side, a back side, and a fully filled thru silicon via, a portion of the fully filled thru silicon via protruding from the back side of the upper die. A lower die includes a front side, a back side, and a partially filled thru silicon via formed to define a via opening exposed to the front side of the die, a portion of the partially filled thru silicon via protruding from the back side of the lower die. An interconnect bonds an outer surface of the protruding portion of the upper die thru silicon via with an inner surface of via opening in the lower die.Type: ApplicationFiled: February 11, 2009Publication date: August 12, 2010Inventor: Satyendra Singh CHAUHAN
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Publication number: 20100062567Abstract: In a method and system for fabricating a semiconductor device (100) having a package-on-package structure, a base laminate substrate (BLS) (110) is formed to include a base center portion (112) and a peripheral portion (114) separated by a barrier element (120). The barrier element (120) forms a peripheral wall (118) to surround the base center portion (112). A frame shaped top laminate substrate (TLS) (130) is disposed over the peripheral portion (114) of the BLS (110). The TLS (130) has an open top center portion (132) matching the base center portion (112) surrounded by the peripheral wall (118) to form a cavity (140). A plurality of conductive bumps (150) each disposed between a top contact pad (134) of the TLS and a base contact pad (116) of the peripheral portion (114) of the BLS (110) are formed to provide electrical and mechanical coupling therebetween. The barrier element (120) forms a seal between the cavity (140) and the plurality of conductive bumps (150).Type: ApplicationFiled: November 16, 2009Publication date: March 11, 2010Applicant: TEXAS INSTRUMENTS INCORPORATEDInventors: Prema PALANIAPPAN, Masood MURTUZA, Satyendra Singh CHAUHAN
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Patent number: 7635914Abstract: In a method and system for fabricating a semiconductor device (100) having a package-on-package structure, a base laminate substrate (BLS) (110) is formed to include a base center portion (112) and a peripheral portion (114) separated by a barrier element (120). The barrier element (120) forms a peripheral wall (118) to surround the base center portion (112). A frame shaped top laminate substrate (TLS) (130) is disposed over the peripheral portion (114) of the BLS (110). The TLS (130) has an open top center portion (132) matching the base center portion (112) surrounded by the peripheral wall (118) to form a cavity (140). A plurality of conductive bumps (150) each disposed between a top contact pad (134) of the TLS and a base contact pad (116) of the peripheral portion (114) of the BLS (110) are formed to provide electrical and mechanical coupling therebetween. The barrier element (120) forms a seal between the cavity (140) and the plurality of conductive bumps (150).Type: GrantFiled: May 17, 2007Date of Patent: December 22, 2009Assignee: Texas Instruments IncorporatedInventors: Prema Palaniappan, Masood Murtuza, Satyendra Singh Chauhan
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Publication number: 20090302438Abstract: An integrated circuit (IC) includes a substrate having a top semiconductor surface and a bottom surface, and integrated circuitry including an analog subcircuit and at least one digital subcircuit formed on the top semiconductor surface. A plurality of through substrate vias (TSVs) extend through the substrate. At least one integrated Faraday shield includes a top and a bottom electrically conducting member that are coupled by the TSVs which surround the analog subcircuit and/or the digital subcircuit. At least one voltage regulator supplies a regulated power supply voltage that is coupled to the integrated Faraday shield that surrounds the analog subcircuit.Type: ApplicationFiled: June 2, 2009Publication date: December 10, 2009Applicant: TEXAS INSTRUMENTS INCORPORATEDInventors: SATYENDRA SINGH CHAUHAN, GREGORY E. HOWARD
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Publication number: 20080283992Abstract: In a method and system for fabricating a semiconductor device (100) having a package-on-package structure, a base laminate substrate (BLS) (110) is formed to include a base center portion (112) and a peripheral portion (114) separated by a barrier element (120). The barrier element (120) forms a peripheral wall (118) to surround the base center portion (112). A frame shaped top laminate substrate (TLS) (130) is disposed over the peripheral portion (114) of the BLS (110). The TLS (130) has an open top center portion (132) matching the base center portion (112) surrounded by the peripheral wall (118) to form a cavity (140). A plurality of conductive bumps (150) each disposed between a top contact pad (134) of the TLS and a base contact pad (116) of the peripheral portion (114) of the BLS (110) are formed to provide electrical and mechanical coupling therebetween. The barrier element (120) forms a seal between the cavity (140) and the plurality of conductive bumps (150).Type: ApplicationFiled: May 17, 2007Publication date: November 20, 2008Applicant: Texas Instruments IncorporatedInventors: Prema Palaniappan, Masood Murtuza, Satyendra Singh Chauhan
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Publication number: 20080280394Abstract: A method of making integrated circuit packages using a conductive plate as a substrate includes forming a partial circuit pattern on one side of the conductive plate by stamping or selectively removing a portion of the conductive plate through part of its thickness, and then electrically coupling semiconductor dies to the formed patterns on the conductive plate. The method further includes encapsulating at least a portion of the dies and the conductive plate with an encapsulant and removing a portion of the conductive plate from the side opposite the patterned side to form conductive traces based on the formed pattern.Type: ApplicationFiled: May 7, 2008Publication date: November 13, 2008Inventors: Masood Murtuza, Satyendra Singh Chauhan, Donald C. Abbott
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Patent number: 6888255Abstract: In accordance with the present invention, a built-up bump pad structure and method for the same are provided. The bump pad structure includes a substrate, a bump pad disposed upon the substrate, a solder mask disposed upon the substrate defining an opening around the bump pad, and a conductive material deposited upon the bump pad such that the conductive material at least partially fills the opening around the bump pad.Type: GrantFiled: May 30, 2003Date of Patent: May 3, 2005Assignee: Texas Instruments IncorporatedInventors: Masood Murtuza, Muthiah Venkateswaran, Satyendra Singh Chauhan