Patents by Inventor Saurabh Gupta

Saurabh Gupta has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20180181686
    Abstract: A method includes receiving a register-transfer-level description and a gate-level description for an integrated circuit design. The gate-level description includes one or more spare latches implemented as reconfigurable latch filler cells. The method further includes receiving an engineering change order, and, responsive to the engineering change order, adding the at least one additional latch to the register-transfer-level description and, for at least one of the at least one additional latch, selecting one of the one or more spare latches in the register-transfer-level description to yield a selected spare latch. The method further includes, for the selected spare latch, identifying a selected reconfigurable latch filler cell in the gate-level description and replacing the selected reconfigurable latch filler cell with an operational latch in the gate-level description. The method further includes finalizing the integrated circuit design.
    Type: Application
    Filed: March 14, 2018
    Publication date: June 28, 2018
    Inventors: Ayan Datta, Saurabh Gupta, Jayaprakash Udhayakumar, Rajesh Veerabhadraiah, Alok Verma
  • Publication number: 20180181687
    Abstract: A method includes receiving a register-transfer-level description and a gate-level description for an integrated circuit design. The gate-level description includes one or more spare latches implemented as reconfigurable latch filler cells. The method further includes receiving an engineering change order, and, responsive to the engineering change order, adding the at least one additional latch to the register-transfer-level description and, for at least one of the at least one additional latch, selecting one of the one or more spare latches in the register-transfer-level description to yield a selected spare latch. The method further includes, for the selected spare latch, identifying a selected reconfigurable latch filler cell in the gate-level description and replacing the selected reconfigurable latch filler cell with an operational latch in the gate-level description. The method further includes finalizing the integrated circuit design.
    Type: Application
    Filed: March 14, 2018
    Publication date: June 28, 2018
    Inventors: Ayan Datta, Saurabh Gupta, Jayaprakash Udhayakumar, Rajesh Veerabhadraiah, Alok Verma
  • Publication number: 20180158008
    Abstract: A method for enhancing on-premise order management systems (OMS) designed for fulfillment transactions with analytic and optimization technologies and services hosted in a shared multi-tenant software-as-a-service (SaaS) environment, such as a hybrid cloud. The computer-implemented method improves an order management system by leveraging a “punch-out” approach based on user exits to integrate with and augment currently implemented order management processing and transaction flows. Using the hybrid cloud, an entity may retain data such as its accumulated business, sales, test and other data, and then run analytical queries, which can scale to support distributed computing tasks. A framework adaptor/connector is leveraged by the OMS to provide a web client for communicating with and integrating to the SaaS analytics runtime environment, encapsulating all necessary connection pooling, security, and data marshaling complexity away from the order management system to meet strict service response time windows.
    Type: Application
    Filed: November 30, 2017
    Publication date: June 7, 2018
    Inventors: Ajay A. Deshpande, Saurabh Gupta, Arun Hampapur, Ali Koc, Yingjie Li, Xuan Liu, Christopher Milite, Brian L. Quanz, Chek Keong Tan, Dahai Xing, Xiaobo Zheng
  • Patent number: 9971592
    Abstract: A computer implemented method and apparatus for a subscription workflow. The method comprises receiving an input indicative of features of a plurality of software products to enable performance of one or more workflows, wherein the input is indicative of features that are less than all of the features of each software product in the plurality of software products; and enabling the features from the plurality of software products to be utilized on a computer to perform the one or more workflows.
    Type: Grant
    Filed: February 27, 2013
    Date of Patent: May 15, 2018
    Assignee: ADOBE SYSTEMS INCORPORATED
    Inventors: Saurabh Gupta, Aditya Falodiya
  • Patent number: 9965576
    Abstract: A method includes receiving a register-transfer-level description and a gate-level description for an integrated circuit design. The gate-level description includes one or more spare latches implemented as reconfigurable latch filler cells. The method further includes receiving an engineering change order, and, responsive to the engineering change order, adding the at least one additional latch to the register-transfer-level description and, for at least one of the at least one additional latch, selecting one of the one or more spare latches in the register-transfer-level description to yield a selected spare latch. The method further includes, for the selected spare latch, identifying a selected reconfigurable latch filler cell in the gate-level description and replacing the selected reconfigurable latch filler cell with an operational latch in the gate-level description. The method further includes finalizing the integrated circuit design.
    Type: Grant
    Filed: July 21, 2017
    Date of Patent: May 8, 2018
    Assignee: International Business Machines Corporation
    Inventors: Ayan Datta, Saurabh Gupta, Jayaprakash Udhayakumar, Rajesh Veerabhadraiah, Alok Verma
  • Patent number: 9953121
    Abstract: A computer-implemented method includes identifying an in initial register-transfer-level description for an integrated circuit design and adding one or more spare latches to the initial register-transfer-level description to yield a modified register-transfer-level description for the integrated circuit design. The computer-implemented method further includes performing placement and routing for the modified register-transfer-level description to yield a gate-level description for the integrated circuit design. The one or more spare latches exist in said gate-level description. The computer-implemented method further includes converting at least one of the one or more spare latches in the gate-level description into a reconfigurable latch filler cell to yield a modified gate-level description for the integrated circuit design and finalizing the integrated circuit design. A corresponding computer program product and computer system are also disclosed.
    Type: Grant
    Filed: May 3, 2016
    Date of Patent: April 24, 2018
    Assignee: International Business Machines Corporation
    Inventors: Ayan Datta, Saurabh Gupta, Jayaprakash Udhayakumar, Rajesh Veerabhadraiah, Alok Verma
  • Patent number: 9954742
    Abstract: A method performed in a first network node, includes the first network node receiving, from a second network node, a request specifying a user account and a media content. The method further includes the first network node retrieving, from a database, a database object associated with the user account, the database object including a first parameter associated with a non-monetary balance. The method further includes the first network node retrieving, from the database, at least one predefined rule associated with the media content. The method further includes the first network node determining an advice of charge using the database object and the at least one predefined rule, the advice of charge specifying a deduction from the non-monetary balance for downloading the media content. The method also includes the first network node transmitting the advice of charge to the second network node.
    Type: Grant
    Filed: September 24, 2014
    Date of Patent: April 24, 2018
    Assignee: Telefonaktiebolaget LM Ericsson (Publ)
    Inventors: Saket Rustagi, Saurabh Gupta
  • Patent number: 9953096
    Abstract: A computer implemented method and system for organizing file location bookmarks of navigations within corresponding applications. A plurality of navigation histories relating to an application are captured, in response to a user navigating a file system using an application and selecting resource locations within corresponding directories of the file system for saving. The selected locations of the navigation history are displayed on a user interface (UI) of the computer. The selected locations of the navigation history are updated and displayed, responsive to the selections of the user.
    Type: Grant
    Filed: June 26, 2015
    Date of Patent: April 24, 2018
    Assignee: International Business Machines Corporation
    Inventors: Saurabh Gupta, Sandeep Perumbuduri, Nancy A. Schipon
  • Publication number: 20180082355
    Abstract: A method for continuously tracking business performance impact of order sourcing systems and algorithms that decide how ecommerce orders should be fulfilled by assigning the items of the order to nodes in a fulfillment network such as stores, distribution centers, and third party logistics—to provide automatic root cause analysis and solution recommendations to pre-defined business problems arising from KPI monitoring. A Business Intelligence (BI) dashboard architecture operates with: 1) a monitoring module that continuously monitors business KPIs and creates abnormality alerts; and 2) a root cause analysis module that is designed specifically for each business problem to give real time diagnosis and solution recommendation. The root cause analysis module receives the created alert, and triggers conducting a root cause analysis at an analytics engine. The BI dashboard and user interface enables visualization of the KPI performance and root cause analysis results.
    Type: Application
    Filed: November 30, 2017
    Publication date: March 22, 2018
    Inventors: Shyh-Kwei Chen, Ajay A. Deshpande, Saurabh Gupta, Arun Hampapur, Ali Koc, Yingjie Li, Dingding Lin, Xuan Liu, Christopher S. Milite, Brian L. Quanz, Chek Keong Tan, Dahai Xing, Xiaobo Zheng
  • Patent number: 9912474
    Abstract: Methods and apparatus related to performance of telemetry, data gathering, and failure isolation using non-volatile memory are described. In one embodiment, a Non-Volatile Memory (NVM) controller logic stores data in a portion of an NVM device. The portion of the NVM device is determined based at least in part on a type or an identity of a sender of the data. Also, the data is encrypted in accordance with a public key provided by the sender. Other embodiments are also disclosed and claimed.
    Type: Grant
    Filed: September 27, 2013
    Date of Patent: March 6, 2018
    Assignee: Intel Corporation
    Inventors: Saurabh Gupta, Vincent J. Zimmer
  • Patent number: 9864922
    Abstract: A content aware pattern stamping tool that preserves the visual texture of an area within an image when filling the area with a pattern is provided. In one embodiment, the pattern stamping tool analyzes an area to be filled with a pattern to determine textural characteristics of the area. These textural characteristics may include reflectance and shading. Once the pattern stamping tool has determined the textural characteristics of the area, the pattern stamping tool fills the area with the pattern and applies the textural characteristics to the filled area. Through application of the textural characteristics, the pattern stamping tool generates an image that combines the pattern with the original textural characteristics of the area.
    Type: Grant
    Filed: September 10, 2015
    Date of Patent: January 9, 2018
    Assignee: ADOBE Systems Inc.
    Inventors: Sourabh Gupta, Saurabh Gupta, Ajay Bedi
  • Publication number: 20170362543
    Abstract: A delayed-release particle comprising a polymer-based matrix comprising polyvinylpyrrolidone and chitosan, and a hydrophobic benefit agent encapsulated by said polymer-based matrix; and processes and consumer products related thereto.
    Type: Application
    Filed: June 15, 2017
    Publication date: December 21, 2017
    Inventors: Shoucang Shen, Tau Yee, Ron Lim, Saurabh Gupta, Calum Macbeath, Robert Wayne Glenn, JR.
  • Patent number: 9836307
    Abstract: The present disclosure is directed to firmware block dispatch based on fusing. A device may determine firmware blocks to load during initialization of the device based on fuses set in a processing module in the device. A firmware module may comprise at least a nonvolatile (NV) memory including boot code and a firmware information table (FIT). During initialization the boot code may cause the processing module to read fuse information from a fuse module and to determine at least one firmware block to load based on the fuse information. For example, the fuse information may comprise a fuse string and the processing module may compare the fuse string to the FIT table, determine at least one pointer in the FIT table associated with the fuse string and load at least one firmware block based on a location (e.g., offset) in the NV memory identified by the at least one pointer.
    Type: Grant
    Filed: June 24, 2015
    Date of Patent: December 5, 2017
    Assignee: Intel Corporation
    Inventors: Saurabh Gupta, Vincent J. Zimmer, Rajesh Poornachandran
  • Patent number: 9836671
    Abstract: Disclosed herein are technologies directed to discovering semantic similarities between images and text, which can include performing image search using a textual query, performing text search using an image as a query, and/or generating captions for images using a caption generator. A semantic similarity framework can include a caption generator and can be based on a deep multimodal similar model. The deep multimodal similarity model can receive sentences and determine the relevancy of the sentences based on similarity of text vectors generated for one or more sentences to an image vector generated for an image. The text vectors and the image vector can be mapped in a semantic space, and their relevance can be determined based at least in part on the mapping. The sentence associated with the text vector determined to be the most relevant can be output as a caption for the image.
    Type: Grant
    Filed: August 28, 2015
    Date of Patent: December 5, 2017
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Jianfeng Gao, Xiaodong He, Saurabh Gupta, Geoffrey G. Zweig, Forrest Iandola, Li Deng, Hao Fang, Margaret A. Mitchell, John C. Platt, Rupesh Kumar Srivastava
  • Publication number: 20170330211
    Abstract: A method and computer readable medium for selecting order fulfillment nodes within an order fulfillment system. The method determines one or more product-node pairs of an omni-channel order fulfillment system responsive to a received customer order. There is received for each determined product-node pair, a first input including an associated price and a price markdown rate (r) for the product. There is further received for each product-node pair, input representing a current amount of supply availability of the product (w) for a period of time in an inventory; and a first threshold value and a second threshold values defining a supply availability window of the product. The method computes an inventory performance value based on the current w, the defined supply availability window, and one or more the p and r values; and selects a node for customer order fulfillment based on the computed cost of inventory performance value.
    Type: Application
    Filed: May 13, 2016
    Publication date: November 16, 2017
    Inventors: Ajay Deshpande, Saurabh Gupta, Arun Hampapur, Alan King, Ali Koc, Yingjie Li, Xuan Liu, Christopher Milite, Brian L. Quanz, Chek Keong Tan, Dahai Xing, Xiaobo Zheng
  • Publication number: 20170323032
    Abstract: A method includes receiving a register-transfer-level description and a gate-level description for an integrated circuit design. The gate-level description includes one or more spare latches implemented as reconfigurable latch filler cells. The method further includes receiving an engineering change order, and, responsive to the engineering change order, adding the at least one additional latch to the register-transfer-level description and, for at least one of the at least one additional latch, selecting one of the one or more spare latches in the register-transfer-level description to yield a selected spare latch. The method further includes, for the selected spare latch, identifying a selected reconfigurable latch filler cell in the gate-level description and replacing the selected reconfigurable latch filler cell with an operational latch in the gate-level description. The method further includes finalizing the integrated circuit design.
    Type: Application
    Filed: July 21, 2017
    Publication date: November 9, 2017
    Inventors: Ayan Datta, Saurabh Gupta, Jayaprakash Udhayakumar, Rajesh Veerabhadraiah, Alok Verma
  • Publication number: 20170323030
    Abstract: A computer-implemented method includes identifying an in initial register-transfer-level description for an integrated circuit design and adding one or more spare latches to the initial register-transfer-level description to yield a modified register-transfer-level description for the integrated circuit design. The computer-implemented method further includes performing placement and routing for the modified register-transfer-level description to yield a gate-level description for the integrated circuit design. The one or more spare latches exist in said gate-level description. The computer-implemented method further includes converting at least one of the one or more spare latches in the gate-level description into a reconfigurable latch filler cell to yield a modified gate-level description for the integrated circuit design and finalizing the integrated circuit design. A corresponding computer program product and computer system are also disclosed.
    Type: Application
    Filed: May 3, 2016
    Publication date: November 9, 2017
    Inventors: Ayan Datta, Saurabh Gupta, Jayaprakash Udhayakumar, Rajesh Veerabhadraiah, Alok Verma
  • Publication number: 20170304307
    Abstract: The present invention relates to Orally Disintegrating Tablets (ODT) of Tofacitinib and its pharmaceutically acceptable salts and the process to produce the ODT. The invention further relates to ODTs comprising Tofacitinib and its pharmaceutically acceptable salts, at least one sweetening agent, at least one disintegrant and optionally other excipients. The weight of the Orally Disintegrating tablets is 200 mg or less. The invention further relates to Orally Disintegrating Tablets of Tofacitinib Citrate.
    Type: Application
    Filed: June 24, 2016
    Publication date: October 26, 2017
    Applicant: Unichem Laboratories Limited
    Inventors: Saurabh Gupta, Saiesh P. Phaldesai, NSK. Senthil Kumar, Milind Vinayak Sathe
  • Publication number: 20170297195
    Abstract: A method for toy robot programming, the toy robot including a set of sensors, the method including, at a user device remote from the toy robot: receiving sensor measurements from the toy robot during physical robot manipulation; in response to detecting a programming trigger event, automatically converting the sensor measurements into a series of puppeted programming inputs; and displaying graphical representations of the set of puppeted programming inputs on a programming interface application on the user device.
    Type: Application
    Filed: June 28, 2017
    Publication date: October 19, 2017
    Inventors: Saurabh Gupta, Vikas Gupta
  • Patent number: D807441
    Type: Grant
    Filed: July 2, 2015
    Date of Patent: January 9, 2018
    Assignee: Play-i, Inc.
    Inventors: Saurabh Gupta, John Moretti, Vikas Gupta