Patents by Inventor Saurin Patel
Saurin Patel has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230208748Abstract: Techniques for detecting path failures and reducing packet loss as a result of such failures are described for use within a data center or other environment. For example, a source and/or destination access node may create and/or maintain information about health and/or connectivity for a plurality of ports or paths between the source and destination device and core switches. The source access node may spray packets over a number of paths between the source access node and the destination access node. The source access node may use the information about connectivity for the paths between the source or destination access nodes and the core switches to limit the paths over which packets are sprayed. The source access node may spray packets over paths between the source access node and the destination access node that are identified as healthy, while avoiding paths that have been identified as failed.Type: ApplicationFiled: February 27, 2023Publication date: June 29, 2023Inventors: Deepak Goel, Pradeep Sindhu, Ayaskant Pani, Srihari Raju Vegesna, Narendra Jayawant Gathoo, John David Huber, Rohit Sunkam Ramanujam, Saurin Patel
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Patent number: 11601359Abstract: Techniques for detecting path failures and reducing packet loss as a result of such failures are described for use within a data center or other environment. For example, a source and/or destination access node may create and/or maintain information about health and/or connectivity for a plurality of ports or paths between the source and destination device and core switches. The source access node may spray packets over a number of paths between the source access node and the destination access node. The source access node may use the information about connectivity for the paths between the source or destination access nodes and the core switches to limit the paths over which packets are sprayed. The source access node may spray packets over paths between the source access node and the destination access node that are identified as healthy, while avoiding paths that have been identified as failed.Type: GrantFiled: March 29, 2021Date of Patent: March 7, 2023Assignee: FUNGIBLE, INC.Inventors: Deepak Goel, Pradeep Sindhu, Ayaskant Pani, Srihari Raju Vegesna, Narendra Jayawant Gathoo, John David Huber, Rohit Sunkam Ramanujam, Saurin Patel
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Patent number: 11082366Abstract: An apparatus and method for queuing data to a memory buffer. The method includes selecting a queue from a plurality of queues; receiving a token of data from the selected queue and requesting, by a queue module, addresses and pointers from a buffer manager for addresses allocated by the buffer manager for storing the token of data. Subsequently, a memory list is accessed by the buffer manager and addresses and pointers are generated to allocated addresses in the memory list which comprises a plurality of linked memory lists for additional address allocation. The method further includes writing into the accessed memory list the pointers for the allocated address where the pointers link together allocated addresses; and migrating to other memory lists for additional address allocations upon receipt of subsequent tokens of data from the queue; and generating additional pointers linking together the allocated addresses in the other memory lists.Type: GrantFiled: October 7, 2019Date of Patent: August 3, 2021Assignee: Marvell Asia Pte, Ltd.Inventors: Vamsi Panchagnula, Saurin Patel, Keqin Han, Tsahi Daniel
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Publication number: 20210218665Abstract: Techniques for detecting path failures and reducing packet loss as a result of such failures are described for use within a data center or other environment. For example, a source and/or destination access node may create and/or maintain information about health and/or connectivity for a plurality of ports or paths between the source and destination device and core switches. The source access node may spray packets over a number of paths between the source access node and the destination access node. The source access node may use the information about connectivity for the paths between the source or destination access nodes and the core switches to limit the paths over which packets are sprayed. The source access node may spray packets over paths between the source access node and the destination access node that are identified as healthy, while avoiding paths that have been identified as failed.Type: ApplicationFiled: March 29, 2021Publication date: July 15, 2021Inventors: Deepak Goel, Pradeep Sindhu, Ayaskant Pani, Srihari Raju Vegesna, Narendra Jayawant Gathoo, John David Huber, Rohit Sunkam Ramanujam, Saurin Patel
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Patent number: 11038993Abstract: Aspects of this disclosure describes techniques for parsing network packets, processing network packets, and modifying network packets before forwarding the modified network packets over a network. The present disclosure describes a system that, in some examples, parses network packets, generates data describing or specifying attributes of the network packet, identifies operations to be performed when processing a network packet, performs the identified operations, generates data describing or specifying how to modify and/or forward the network packet, modifies the network packet, and outputs the modified packet to another device or system, such as a switch.Type: GrantFiled: March 13, 2019Date of Patent: June 15, 2021Assignee: FUNGIBLE, INC.Inventors: Deepak Goel, Jean-Marc Frailong, Srihari Raju Vegesna, Stimit Kishor Oak, Rohit Sunkam Ramanujam, John David Huber, Hariharan Lakshminarayanan Thantry, Vikas Minglani, Saurin Patel, Sureshkumar Nedunchezhian
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Patent number: 10965586Abstract: Techniques for detecting path failures and reducing packet loss as a result of such failures are described for use within a data center or other environment. For example, a source and/or destination access node may create and/or maintain information about health and/or connectivity for a plurality of ports or paths between the source and destination device and core switches. The source access node may spray packets over a number of paths between the source access node and the destination access node. The source access node may use the information about connectivity for the paths between the source or destination access nodes and the core switches to limit the paths over which packets are sprayed. The source access node may spray packets over paths between the source access node and the destination access node that are identified as healthy, while avoiding paths that have been identified as failed.Type: GrantFiled: September 28, 2018Date of Patent: March 30, 2021Assignee: Fungible, Inc.Inventors: Deepak Goel, Pradeep Sindhu, Ayaskant Pani, Srihari Raju Vegesna, Narendra Jayawant Gathoo, John David Huber, Rohit Sunkam Ramanujam, Saurin Patel
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Patent number: 10567273Abstract: An apparatus for routing multicast data packets, the apparatus includes an ingress port to receive data streams of multicast data packets and status data about egress ports available to transmit the multicast traffic data streams. A processor coupled to the ingress port, to identify source data of the multicast data packets of the data streams to match the multicast data packets with available egress ports. The processor to determine, using the identified source and status data which of the multicast data packets matches the available egress ports. The processor to select a first data path coupled to the egress port to transmit the matched multicast data packets to available egress ports where the selected first data path is configured to enable the direct transmission of the matched multicast data packets to available egress ports.Type: GrantFiled: March 27, 2015Date of Patent: February 18, 2020Assignee: Cavium, LLCInventors: Vamsi Panchagnula, Saurin Patel, Keqin Han
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Publication number: 20200044989Abstract: An apparatus and method for queuing data to a memory buffer. The method includes selecting a queue from a plurality of queues; receiving a token of data from the selected queue and requesting, by a queue module, addresses and pointers from a buffer manager for addresses allocated by the buffer manager for storing the token of data. Subsequently, a memory list is accessed by the buffer manager and addresses and pointers are generated to allocated addresses in the memory list which comprises a plurality of linked memory lists for additional address allocation. The method further includes writing into the accessed memory list the pointers for the allocated address where the pointers link together allocated addresses; and migrating to other memory lists for additional address allocations upon receipt of subsequent tokens of data from the queue; and generating additional pointers linking together the allocated addresses in the other memory lists.Type: ApplicationFiled: October 7, 2019Publication date: February 6, 2020Inventors: Vamsi PANCHAGNULA, Saurin PATEL, Ken HAN, Daniel TSAHI
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Patent number: 10484311Abstract: An apparatus and method for queuing data to a memory buffer. The method includes selecting a queue from a plurality of queues; receiving a token of data from the selected queue and requesting, by a queue module, addresses and pointers from a buffer manager for addresses allocated by the buffer manager for storing the token of data. Subsequently, a memory list is accessed by the buffer manager and addresses and pointers are generated to allocated addresses in the memory list which comprises a plurality of linked memory lists for additional address allocation. The method further includes writing into the accessed memory list the pointers for the allocated address where the pointers link together allocated addresses; and migrating to other memory lists for additional address allocations upon receipt of subsequent tokens of data from the queue; and generating additional pointers linking together the allocated addresses in the other memory lists.Type: GrantFiled: March 31, 2015Date of Patent: November 19, 2019Assignee: CAVIUM, LLCInventors: Vamsi Panchagnula, Saurin Patel, Keqin Han, Tsahi Daniel
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Publication number: 20190289102Abstract: Aspects of this disclosure describes techniques for parsing network packets, processing network packets, and modifying network packets before forwarding the modified network packets over a network. The present disclosure describes a system that, in some examples, parses network packets, generates data describing or specifying attributes of the network packet, identifies operations to be performed when processing a network packet, performs the identified operations, generates data describing or specifying how to modify and/or forward the network packet, modifies the network packet, and outputs the modified packet to another device or system, such as a switch.Type: ApplicationFiled: March 13, 2019Publication date: September 19, 2019Inventors: Deepak Goel, Jean-Marc Frailong, Srihari Raju Vegesna, Stimit Kishor Oak, Rohit Sunkam Ramanujam, John David Huber, Hariharan Lakshminarayanan Thantry, Vikas Minglani, Saurin Patel, Sureshkumar Nedunchezhian
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Publication number: 20190104057Abstract: Techniques for detecting path failures and reducing packet loss as a result of such failures are described for use within a data center or other environment. For example, a source and/or destination access node may create and/or maintain information about health and/or connectivity for a plurality of ports or paths between the source and destination device and core switches. The source access node may spray packets over a number of paths between the source access node and the destination access node. The source access node may use the information about connectivity for the paths between the source or destination access nodes and the core switches to limit the paths over which packets are sprayed. The source access node may spray packets over paths between the source access node and the destination access node that are identified as healthy, while avoiding paths that have been identified as failed.Type: ApplicationFiled: September 28, 2018Publication date: April 4, 2019Inventors: Deepak Goel, Pradeep Sindhu, Ayaskant Pani, Srihari Raju Vegesna, Narendra Jayawant Gathoo, John David Huber, Rohit Sunkam Ramanujam, Saurin Patel
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Patent number: 10082538Abstract: A testbench for testing a device under test (DUT), wherein the testbench has a verification environment including a reference model, a scoreboard and a customized agent for each interface that the DUT needs to receive input from and/or transmit output on. The testbench system is able to be generated by a testbench builder that automatically creates a scoreboard, a reference model, a dispatcher and generic agents including generic drivers, loopback ports, sequencers and/or generic monitors for each interface and then automatically customize the generic agents based on their corresponding interface such that the agents meet the requirements of the interface for the DUT.Type: GrantFiled: February 9, 2015Date of Patent: September 25, 2018Assignee: Cavium, Inc.Inventors: Nimalan Siva, Keqin Kenneth Han, Polasanapalli Sri Devi, Saurin Patel
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Patent number: 9870173Abstract: An optimized design of n-write/1-read port memory comprises a memory unit including a plurality of memory banks each having one write port and one read port configured to write data to and read data from the memory banks, respectively. The memory further comprises a plurality of write interfaces configured to carry concurrent write requests to the memory unit for a write operation, wherein the first write request is always presented by its write interface directly to a crossbar, wherein the rest of the write requests are each fed through a set of temporary memory modules connected in a sequence before being presented to the crossbar. The crossbar is configured to accept the first write request directly and fetch the rest of the write requests from one of the memory modules in the set and route each of the write requests to one of the memory banks in the memory unit.Type: GrantFiled: February 19, 2016Date of Patent: January 16, 2018Assignee: CAVIUM, INC.Inventors: Saurin Patel, Weihuang Wang
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Patent number: 9817067Abstract: A testbench for testing a device under test (DUT), wherein the testbench has a verification environment including a reference model, a scoreboard and a customized agent for each interface that the DUT needs to receive input from and/or transmit output on. The testbench system is able to be generated by a testbench builder that automatically creates a scoreboard, a reference model, a dispatcher and generic agents including generic drivers, loopback ports, sequencers and/or generic monitors for each interface and then automatically customize the generic agents based on their corresponding interface such that the agents meet the requirements of the interface for the DUT.Type: GrantFiled: March 27, 2015Date of Patent: November 14, 2017Assignee: Cavium, Inc.Inventors: Saurin Patel, Nimalan Siva, Keqin Kenneth Han
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Patent number: 9778315Abstract: A testbench for testing a device under test (DUT), wherein the testbench has a verification environment including a reference model, a scoreboard and a customized agent for each interface that the DUT needs to receive input from and/or transmit output on. The testbench system is able to be generated by a testbench builder that automatically creates a scoreboard, a reference model, a dispatcher and generic agents including generic drivers, loopback ports, sequencers and/or generic monitors for each interface and then automatically customize the generic agents based on their corresponding interface such that the agents meet the requirements of the interface for the DUT.Type: GrantFiled: February 9, 2015Date of Patent: October 3, 2017Assignee: Cavium, Inc.Inventors: Nimalan Siva, Keqin Kenneth Han, Saurin Patel, Mohan Balan
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Publication number: 20170242624Abstract: An optimized design of n-write/1-read port memory comprises a memory unit including a plurality of memory banks each having one write port and one read port configured to write data to and read data from the memory banks, respectively. The memory further comprises a plurality of write interfaces configured to carry concurrent write requests to the memory unit for a write operation, wherein the first write request is always presented by its write interface directly to a crossbar, wherein the rest of the write requests are each fed through a set of temporary memory modules connected in a sequence before being presented to the crossbar. The crossbar is configured to accept the first write request directly and fetch the rest of the write requests from one of the memory modules in the set and route each of the write requests to one of the memory banks in the memory unit.Type: ApplicationFiled: February 19, 2016Publication date: August 24, 2017Inventors: Saurin Patel, Weihuang Wang
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Patent number: 9547041Abstract: A testbench for testing a device under test (DUT), wherein the testbench has a verification environment including a reference model, a scoreboard and a customized agent for each interface that the DUT needs to receive input from and/or transmit output on. The testbench system is able to be generated by a testbench builder that automatically creates a scoreboard, a reference model, a dispatcher and generic agents including generic drivers, loopback ports, sequencers and/or generic monitors for each interface and then automatically customize the generic agents based on their corresponding interface such that the agents meet the requirements of the interface for the DUT.Type: GrantFiled: March 27, 2015Date of Patent: January 17, 2017Assignee: Cavium, Inc.Inventors: Nimalan Siva, Keqin Kenneth Han, Saurin Patel
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Patent number: 9531848Abstract: Embodiments of the apparatus for modifying packet headers relate to programmable modifications of packets by applying commands to generalized protocol headers. Each protocol header of incoming packets is represented in a generic format specific to that protocol to enable modifications to packet headers. Missing fields from a protocol header are detected, and the protocol header is expanded to a maximum size such that the protocol header contains all possible fields of that protocol, including the missing fields. Each of the fields has the same offset irrespective of which variation of the protocol the protocol header corresponds to. Modification uses a set of commands that is applied to expanded protocol headers. All of the commands are thus generic as these commands are independent of incoming headers (e.g., size and protocol).Type: GrantFiled: June 19, 2014Date of Patent: December 27, 2016Assignee: Cavium, Inc.Inventors: Chirinjeev Singh, Tsahi Daniel, Gerald Schmidt, Saurin Patel
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Patent number: 9531849Abstract: Embodiments of the apparatus for modifying packet headers relate to pointer structure for splitting a packet into individual layers and for intelligently stitching them back together. The pointer structure includes N+1 layer pointers to N+1 protocol headers. The pointer structure also includes a total size of all headers. A rewrite engine uses the layer pointers to extract the first N corresponding protocol layers within the packet for modification. The rewrite engine uses the layer pointers to form an end point, which together with the total size of all headers is associated with a body of the headers. The body of the headers is a portion of headers that are not modified by the rewrite engine. After all the modifications are performed and modified headers are compressed, the modified layer pointers are used to stitch the modified headers back together with the body of the headers.Type: GrantFiled: June 19, 2014Date of Patent: December 27, 2016Assignee: Cavium, Inc.Inventors: Chirinjeev Singh, Tsahi Daniel, Gerald Schmidt, Saurin Patel
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Patent number: 9506982Abstract: A testbench for testing a device under test (DUT), wherein the testbench has a verification environment including a reference model, a scoreboard and a customized agent for each interface that the DUT needs to receive input from and/or transmit output on. The testbench system is able to be generated by a testbench builder that automatically creates a scoreboard, a reference model, a dispatcher and generic agents including generic drivers, loopback ports, sequencers and/or generic monitors for each interface and then automatically customize the generic agents based on their corresponding interface such that the agents meet the requirements of the interface for the DUT.Type: GrantFiled: February 9, 2015Date of Patent: November 29, 2016Assignee: Cavium, Inc.Inventors: Keqin Kenneth Han, Nimalan Siva, Sri Devi Polasanapalli, Saurin Patel