Patents by Inventor Saurin Patel

Saurin Patel has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9497294
    Abstract: Embodiments of the apparatus for modifying packet headers relate to a packet generalization scheme that maintains information across protocol layers of packets. The packet generalization scheme uses a protocol table that includes layer information for all possible protocol layer combinations. The protocol layer combinations in the protocol table are manually configured through software. Each protocol layer combination in the protocol table is uniquely identified by a PktID. A rewrite engine of a network device receives the PktID for a packet and uses that unique identifier as key to the protocol table to access information for each protocol layer of the packet that the rewrite engine requires during modification of the packet. The packet generalization scheme eliminates the need for a parser engine of the network device to pass parsed data to the rewrite engine, which is resource intensive.
    Type: Grant
    Filed: June 19, 2014
    Date of Patent: November 15, 2016
    Assignee: CAVIUM, INC.
    Inventors: Chirinjeev Singh, Tsahi Daniel, Gerald Schmidt, Saurin Patel
  • Publication number: 20160294735
    Abstract: An apparatus and method for queuing data to a memory buffer. The method includes selecting a queue from a plurality of queues; receiving a token of data from the selected queue and requesting, by a queue module, addresses and pointers from a buffer manager for addresses allocated by the buffer manager for storing the token of data. Subsequently, a memory list is accessed by the buffer manager and addresses and pointers are generated to allocated addresses in the memory list which comprises a plurality of linked memory lists for additional address allocation. The method further includes writing into the accessed memory list the pointers for the allocated address where the pointers link together allocated addresses; and migrating to other memory lists for additional address allocations upon receipt of subsequent tokens of data from the queue; and generating additional pointers linking together the allocated addresses in the other memory lists.
    Type: Application
    Filed: March 31, 2015
    Publication date: October 6, 2016
    Inventors: Vamsi PANCHAGNULA, Saurin PATEL, Keqin HAN, Tsahi DANIEL
  • Publication number: 20160285744
    Abstract: An apparatus for routing multicast data packets, the apparatus includes an ingress port to receive data streams of multicast data packets and status data about egress ports available to transmit the multicast traffic data streams. A processor coupled to the ingress port, to identify source data of the multicast data packets of the data streams to match the multicast data packets with available egress ports. The processor to determine, using the identified source and status data which of the multicast data packets matches the available egress ports. The processor to select a first data path coupled to the egress port to transmit the matched multicast data packets to available egress ports where the selected first data path is configured to enable the direct transmission of the matched multicast data packets to available egress ports.
    Type: Application
    Filed: March 27, 2015
    Publication date: September 29, 2016
    Inventors: Vamsi PANCHAGNULA, Saurin PATEL, Keqin HAN
  • Publication number: 20160139205
    Abstract: A testbench for testing a device under test (DUT), wherein the testbench has a verification environment including a reference model, a scoreboard and a customized agent for each interface that the DUT needs to receive input from and/or transmit output on. The testbench system is able to be generated by a testbench builder that automatically creates a scoreboard, a reference model, a dispatcher and generic agents including generic drivers, loopback ports, sequencers and/or generic monitors for each interface and then automatically customize the generic agents based on their corresponding interface such that the agents meet the requirements of the interface for the DUT.
    Type: Application
    Filed: February 9, 2015
    Publication date: May 19, 2016
    Inventors: Nimalan Siva, Keqin Kenneth Han, Polasanapalli Sri Devi, Saurin Patel
  • Publication number: 20160140006
    Abstract: A testbench for testing a device under test (DUT), wherein the testbench has a verification environment including a reference model, a scoreboard and a customized agent for each interface that the DUT needs to receive input from and/or transmit output on. The testbench system is able to be generated by a testbench builder that automatically creates a scoreboard, a reference model, a dispatcher and generic agents including generic drivers, loopback ports, sequencers and/or generic monitors for each interface and then automatically customize the generic agents based on their corresponding interface such that the agents meet the requirements of the interface for the DUT.
    Type: Application
    Filed: February 9, 2015
    Publication date: May 19, 2016
    Inventors: Nimalan Siva, Keqin Kenneth Han, Saurin Patel, Mohan Balan
  • Publication number: 20160140285
    Abstract: A testbench for testing a device under test (DUT), wherein the testbench has a verification environment including a reference model, a scoreboard and a customized agent for each interface that the DUT needs to receive input from and/or transmit output on. The testbench system is able to be generated by a testbench builder that automatically creates a scoreboard, a reference model, a dispatcher and generic agents including generic drivers, loopback ports, sequencers and/or generic monitors for each interface and then automatically customize the generic agents based on their corresponding interface such that the agents meet the requirements of the interface for the DUT.
    Type: Application
    Filed: February 9, 2015
    Publication date: May 19, 2016
    Inventors: Keqin Kenneth Han, Nimalan Siva, Polasanapalli Sri Devi, Saurin Patel
  • Publication number: 20160140286
    Abstract: A testbench for testing a device under test (DUT), wherein the testbench has a verification environment including a reference model, a scoreboard and a customized agent for each interface that the DUT needs to receive input from and/or transmit output on. The testbench system is able to be generated by a testbench builder that automatically creates a scoreboard, a reference model, a dispatcher and generic agents including generic drivers, loopback ports, sequencers and/or generic monitors for each interface and then automatically customize the generic agents based on their corresponding interface such that the agents meet the requirements of the interface for the DUT.
    Type: Application
    Filed: March 27, 2015
    Publication date: May 19, 2016
    Inventors: Nimalan Siva, Keqin Kenneth Han, Saurin Patel
  • Publication number: 20160139202
    Abstract: A testbench for testing a device under test (DUT), wherein the testbench has a verification environment including a reference model, a scoreboard and a customized agent for each interface that the DUT needs to receive input from and/or transmit output on. The testbench system is able to be generated by a testbench builder that automatically creates a scoreboard, a reference model, a dispatcher and generic agents including generic drivers, loopback ports, sequencers and/or generic monitors for each interface and then automatically customize the generic agents based on their corresponding interface such that the agents meet the requirements of the interface for the DUT.
    Type: Application
    Filed: March 27, 2015
    Publication date: May 19, 2016
    Inventors: Saurin Patel, Nimalan Siva, Keqin Kenneth Han
  • Publication number: 20160140284
    Abstract: A testbench for testing a device under test (DUT), wherein the testbench has a verification environment including a reference model, a scoreboard and a customized agent for each interface that the DUT needs to receive input from and/or transmit output on. The testbench system is able to be generated by a testbench builder that automatically creates a scoreboard, a reference model, a dispatcher and generic agents including generic drivers, loopback ports, sequencers and/or generic monitors for each interface and then automatically customize the generic agents based on their corresponding interface such that the agents meet the requirements of the interface for the DUT.
    Type: Application
    Filed: February 9, 2015
    Publication date: May 19, 2016
    Inventors: Keqin Kenneth Han, Nimalan Siva, Mohan Balan, Saurin Patel
  • Publication number: 20160139204
    Abstract: A testbench for testing a device under test (DUT), wherein the testbench has a verification environment including a reference model, a scoreboard and a customized agent for each interface that the DUT needs to receive input from and/or transmit output on. The testbench system is able to be generated by a testbench builder that automatically creates a scoreboard, a reference model, a dispatcher and generic agents including generic drivers, loopback ports, sequencers and/or generic monitors for each interface and then automatically customize the generic agents based on their corresponding interface such that the agents meet the requirements of the interface for the DUT.
    Type: Application
    Filed: February 9, 2015
    Publication date: May 19, 2016
    Inventors: Keqin Kenneth Han, Nimalan Siva, Saurin Patel, Polasanapalli Sri Devi
  • Patent number: 9330227
    Abstract: A testbench for testing a device under test (DUT), wherein the testbench has a verification environment including a reference model, a scoreboard and a customized agent for each interface that the DUT needs to receive input from and/or transmit output on. The testbench system is able to be generated by a testbench builder that automatically creates a scoreboard, a reference model, a dispatcher and generic agents including generic drivers, loopback ports, sequencers and/or generic monitors for each interface and then automatically customize the generic agents based on their corresponding interface such that the agents meet the requirements of the interface for the DUT.
    Type: Grant
    Filed: February 9, 2015
    Date of Patent: May 3, 2016
    Assignee: Cavium Inc.
    Inventors: Keqin Kenneth Han, Nimalan Siva, Mohan Balan, Saurin Patel
  • Publication number: 20150373159
    Abstract: Embodiments of the apparatus for modifying packet headers relate to programmable modifications of packets by applying commands to generalized protocol headers. Each protocol header of incoming packets is represented in a generic format specific to that protocol to enable modifications to packet headers. Missing fields from a protocol header are detected, and the protocol header is expanded to a maximum size such that the protocol header contains all possible fields of that protocol, including the missing fields. Each of the fields has the same offset irrespective of which variation of the protocol the protocol header corresponds to. Modification uses a set of commands that is applied to expanded protocol headers. All of the commands are thus generic as these commands are independent of incoming headers (e.g., size and protocol).
    Type: Application
    Filed: June 19, 2014
    Publication date: December 24, 2015
    Inventors: Chirinjeev Singh, Tsahi Daniel, Gerald Schmidt, Saurin Patel
  • Publication number: 20150373161
    Abstract: Embodiments of the apparatus for modifying packet headers relate to pointer structure for splitting a packet into individual layers and for intelligently stitching them back together. The pointer structure includes N+1 layer pointers to N+1 protocol headers. The pointer structure also includes a total size of all headers. A rewrite engine uses the layer pointers to extract the first N corresponding protocol layers within the packet for modification. The rewrite engine uses the layer pointers to form an end point, which together with the total size of all headers is associated with a body of the headers. The body of the headers is a portion of headers that are not modified by the rewrite engine. After all the modifications are performed and modified headers are compressed, the modified layer pointers are used to stitch the modified headers back together with the body of the headers.
    Type: Application
    Filed: June 19, 2014
    Publication date: December 24, 2015
    Inventors: Chirinjeev Singh, Tsahi Daniel, Gerald Schmidt, Saurin Patel
  • Publication number: 20150373156
    Abstract: Embodiments of the apparatus for modifying packet headers relate to a packet generalization scheme that maintains information across protocol layers of packets. The packet generalization scheme uses a protocol table that includes layer information for all possible protocol layer combinations. The protocol layer combinations in the protocol table are manually configured through software. Each protocol layer combination in the protocol table is uniquely identified by a PktID. A rewrite engine of a network device receives the PktID for a packet and uses that unique identifier as key to the protocol table to access information for each protocol layer of the packet that the rewrite engine requires during modification of the packet. The packet generalization scheme eliminates the need for a parser engine of the network device to pass parsed data to the rewrite engine, which is resource intensive.
    Type: Application
    Filed: June 19, 2014
    Publication date: December 24, 2015
    Inventors: Chirinjeev Singh, Tsahi Daniel, Gerald Schmidt, Saurin Patel