Abstract: In one example a base station for an electronic device comprises a charging station, an audio interface, logic, at least partially including hardware logic, configured to detect a first electronic device within a geographic region proximate the charging device, and in response to detecting the first electronic device 100, to establish a communication link with the first electronic device via a wireless communication channel, activate the audio interface to receive audio input. Other examples may be described.

Abstract: In one example a controller comprises logic, at least partially including hardware logic, configured to receive a signal from a remote electronic device, and in response to the signal, to present an announcement of an incoming call on the remote device, receive an instruction for the incoming call, and in response to a determination that the instruction is a greeting, to buffer the greeting, instruct the remote electronic device to connect the call, and present the greeting on the call. Other examples may be described.

Abstract: In one example a controller comprises logic, at least partially including hardware logic, configured to detect a key phrase in a received audio signal, and in response to the key phrase, to transmit a signal to a personal assistant in a remote electronic device, determine whether an audio input was received, and in response to a determination that additional audio input was received prior to receiving a response from the personal assistant in the remote electronic device, to buffer the audio input in a memory and forward the audio input to the personal assistant in the remote electronic device. Other examples may be described.

Abstract: Systems and methods may provide for determining a sound vibration condition of an ambient environment of a wearable device and determining a motion condition of the wearable device. In addition, one or more automated voice operations may be performed based at least in part on the sound vibration condition and the motion condition. In one example, two or more signals corresponding to the sound vibration condition and the motion condition may be combined.

Abstract: Generally, this disclosure provides devices, systems and methods for cancelling an interfering audio signal. The system may include a mobile device including a microphone configured to capture an acoustic audio signal, the acoustic audio signal a combination of the interfering audio signal and a desired audio signal, the desired audio signal generated by a user of the mobile device. The system may also include a wireless communication module incorporated in the mobile device, to receive a reference signal through a side-channel, the reference signal associated with the interfering audio signal. The system may further include an acoustic echo cancellation module incorporated in the mobile device, the acoustic echo cancellation module to cancel the interfering audio signal from the captured acoustic audio signal, the cancellation based on the reference signal.

Abstract: Apparatus, computer-readable storage medium, and method associated with speech recognition are described. In embodiments, a mobile phone may include a processor; and a speech recognition module coupled with the processor. The voice recognition module may be configured to recognize one or more voice commands and may include first echo cancellation logic and second echo cancellation logic to be selectively employed during recognition of voice commands. Employment of the first and second echo cancellation logic respectively may cause the mobile phone to variably consume a first and second amount of energy, with the second amount of energy being less than the first amount energy.

Abstract: A distributed direct memory access (DMA) method, apparatus, and system is provided within a system on chip (SOC). DMA controller units are distributed to various functional modules desiring direct memory access. The functional modules interface to a systems bus over which the direct memory access occurs. A global buffer memory, to which the direct memory access is desired, is coupled to the system bus. Bus arbitrators are utilized to arbitrate which functional modules have access to the system bus to perform the direct memory access. Once a functional module is selected by the bus arbitrator to have access to the system bus, it can establish a DMA routine with the global buffer memory.

Abstract: A method for processing a database application component modification request includes receiving a request to modify a database application component of a database application, initiating the database application component modification, sending a response including instructions for accessing a database application component definition including the database application component modification, wherein the database application component definition is provided as a locally accessible temporary copy of the database application component.

Abstract: A method for processing a database object information request includes receiving a database object information request. The database object information request includes a session initiation request and a database object schema retrieval request. The method further includes opening a database object information retrieval session, including assigning a session identifier to the database object information retrieval session, retrieving a result set corresponding to the database object information request, further including assigning a moniker to the result set for use in subsequent database object information retrieval, retrieving the requested database object information using the session identifier and the moniker, and providing a database object information response, the database object information response including the requested database object information.

Abstract: A distributed direct memory access (DMA) method, apparatus, and system is provided within a system on chip (SOC). DMA controller units are distributed to various functional modules desiring direct memory access. The functional modules interface to a systems bus over which the direct memory access occurs. A global buffer memory, to which the direct memory access is desired, is coupled to the system bus. Bus arbitrators are utilized to arbitrate which functional modules have access to the system bus to perform the direct memory access. Once a functional module is selected by the bus arbitrator to have access to the system bus, it can establish a DMA routine with the global buffer memory.

Abstract: A distributed direct memory access (DMA) method, apparatus, and system is provided within a system on chip (SOC). DMA controller units are distributed to various functional modules desiring direct memory access. The functional modules interface to a systems bus over which the direct memory access occurs. A global buffer memory, to which the direct memory access is desired, is coupled to the system bus. Bus arbitrators are utilized to arbitrate which functional modules have access to the system bus to perform the direct memory access. Once a functional module is selected by the bus arbitrator to have access to the system bus, it can establish a DMA routine with the global buffer memory.

Abstract: A distributed direct memory access (DMA) method, apparatus, and system is provided within a system on chip (SOC). DMA controller units are distributed to various functional modules desiring direct memory access. The functional modules interface to a systems bus over which the direct memory access occurs. A global buffer memory, to which the direct memory access is desired, is coupled to the system bus. Bus arbitrators are utilized to arbitrate which functional modules have access to the system bus to perform the direct memory access. Once a functional module is selected by the bus arbitrator to have access to the system bus, it can establish a DMA routine with the global buffer memory.

Abstract: A distributed direct memory access (DMA) method, apparatus, and system is provided within a system on chip (SOC). DMA controller units are distributed to various functional modules desiring direct memory access. The functional modules interface to a systems bus over which the direct memory access occurs. A global buffer memory, to which the direct memory access is desired, is coupled to the system bus. Bus arbitrators are utilized to arbitrate which functional modules have access to the system bus to perform the direct memory access. Once a functional module is selected by the bus arbitrator to have access to the system bus, it can establish a DMA routine with the global buffer memory.

Abstract: A distributed direct memory access (DMA) method, apparatus, and system is provided within a system on chip (SOC). DMA controller units are distributed to various functional modules desiring direct memory access. The functional modules interface to a systems bus over which the direct memory access occurs. A global buffer memory, to which the direct memory access is desired, is coupled to the system bus. Bus arbitrators are utilized to arbitrate which functional modules have access to the system bus to perform the direct memory access. Once a functional module is selected by the bus arbitrator to have access to the system bus, it can establish a DMA routine with the global buffer memory.

Abstract: A distributed direct memory access (DMA) method, apparatus, and system is provided within a system on chip (SOC). DMA controller units are distributed to various functional modules desiring direct memory access. The functional modules interface to a systems bus over which the direct memory access occurs. A global buffer memory, to which the direct memory access is desired, is coupled to the system bus. Bus arbitrators are utilized to arbitrate which functional modules have access to the system bus to perform the direct memory access. Once a functional module is selected by the bus arbitrator to have access to the system bus, it can establish a DMA routine with the global buffer memory.

Abstract: A method of controlling an optical signal receiver utilizes three control loops: a first control loop tunes the decision threshold of the receiver when the optical network is in a substantially steady state and a second control loop rapidly switches to a reference decision threshold upon the occurrence of an alarm condition. The invention rapidly switches to a predetermined reference decision threshold to compensate for optical signal changes in eye Q and received power after a protection switch or traffic reroute. After a protection switch, a slower tuning algorithm is used to adjust the decision threshold to a more optimum value. In the third control loop, the optical signal receiver may utilize a peak detector that detects the optical signal peak and a potentiometer that is commanded by a controller to output a commanded percentage of this peak value to adjust the threshold and thereby respond to transients.

Abstract: A network interface between an internal bus and an external bus architecture having one or more external buses includes an external interface engine and an internal interface. The external interface engine (EIE) is coupled to the external bus architecture, where the external interface engine communicates over the external bus architecture in accordance with one or more bus protocols. The internal interface is coupled to the external interface engine and the internal bus, where the internal interface buffers network data between the internal bus and the external bus architecture. In one embodiment, the internal interface includes an internal interface (IIE) coupled to the internal bus, where the IIE defines a plurality of queues for the network data. An intermediate memory module is coupled to the IIE and the EIE, where the intermediate memory module aggregates the network data in accordance with the plurality of queues.

Abstract: A direct memory access (DMA) descriptor table to control DMA of information in a memory is disclosed. The DMA descriptor table includes one or more DMA descriptor lists stored in the memory. Each DMA descriptor lists may include one or more pointers and information regarding the type of data being directly memory accessed. The pointers may point to a starting address in the memory from which to directly memory access data, prior state information, or program code from and to the memory.

Abstract: A method for optimizing an optical transmitter is provided. According to one exemplary method, the optical transmitter is optimized by varying three transmitter parameters including the bias voltage, the crossing level and the peak-to-peak voltage. Once the respective optimal levels for the bias voltage, the crossing level and the peak-to-peak voltage are obtained, the optical transmitter is further checked to ensure that the optical transmitter is able to function properly within certain predetermined system parameters. The optical transmitter is also checked under two limiting scenarios to ensure that the optical transmitter is optimized against two predetermined lengths of optical fiber.

Abstract: A distributed direct memory access (DMA) method, apparatus, and system is provided within a system on chip (SOC). DMA controller units are distributed to various functional modules desiring direct memory access. The functional modules interface to a systems bus over which the direct memory access occurs. A global buffer memory, to which the direct memory access is desired, is coupled to the system bus. Bus arbitrators are utilized to arbitrate which functional modules have access to the system bus to perform the direct memory access. Once a functional module is selected by the bus arbitrator to have access to the system bus, it can establish a DMA routine with the global buffer memory.