Patents by Inventor Sayeef Salahuddin
Sayeef Salahuddin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240136437Abstract: A ferroelectric field-effect transistor having an endurance exceeding 1012 cycles is disclosed. The ferroelectric field-effect transistor includes a substrate, a source disposed over a first region of the semiconductor substrate, a drain disposed over a second region of the substrate, wherein the second region is spaced apart from the first region. The ferroelectric field-effect transistor includes a channel made of a semiconductor material within a third region of the substrate that is between the first region and the second region. The ferroelectric field-effect transistor further includes a gate stack having an interfacial layer disposed over the channel, wherein the interfacial layer has a permittivity that is greater than 3.9, and a layer of ferroelectric material disposed over the interfacial layer.Type: ApplicationFiled: February 22, 2022Publication date: April 25, 2024Inventors: Sayeef Salahuddin, Ava Jiang Tan
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Patent number: 11923341Abstract: An electronic device with embedded access to a high-bandwidth, high-capacity fast-access memory includes (a) a memory circuit fabricated on a first semiconductor die, wherein the memory circuit includes numerous modular memory units, each modular memory unit having (i) a three-dimensional array of storage transistors, and (ii) a group of conductors exposed to a surface of the first semiconductor die, the group of conductors being configured for communicating control, address and data signals associated the memory unit; and (b) a logic circuit fabricated on a second semiconductor die, wherein the logic circuit also includes conductors each exposed at a surface of the second semiconductor die, wherein the first and second semiconductor dies are wafer-bonded, such that the conductors exposed at the surface of the first semiconductor die are each electrically connected to a corresponding one of the conductors exposed to the surface of the second semiconductor die.Type: GrantFiled: September 3, 2021Date of Patent: March 5, 2024Assignee: SUNRISE MEMORY CORPORATIONInventors: Khandker Nazrul Quader, Robert Norman, Frank Sai-keung Lee, Christopher J. Petti, Scott Brad Herner, Siu Lung Chan, Sayeef Salahuddin, Mehrdad Mofidi, Eli Harari
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Publication number: 20240062739Abstract: An acoustically driven ferromagnetic resonance (ADFMR) device has a piezoelectric element comprised of piezoelectric material, first and second electrodes arranged in a vertical stack with the piezoelectric element to activate the piezoelectric element to generate an acoustic wave, a radio frequency voltage source electrically connected to the first electrode, a magnet comprised of a magnetostrictive material in the vertical stack with the first and second electrodes and the piezoelectric element to receive the acoustic wave, wherein the acoustic wave resonates at a ferromagnetic resonance of the magnetostrictive material, and a readout circuit to detect a change in the acoustic wave by detecting one of an output voltage amplitude, a change in impedance or a reflection of the acoustic wave in the magnet to measure an unknown magnetic field in which the ADFMR device resides and as experienced at the magnetostrictive element.Type: ApplicationFiled: October 27, 2023Publication date: February 22, 2024Inventors: SAYEEF SALAHUDDIN, DOMINIC E. LABANOWSKI
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Patent number: 11837211Abstract: An acoustically driven ferromagnetic resonance (ADFMR) device includes a piezoelectric element, a pair of transducers arranged to activate the piezoelectric element to generate an acoustic wave, a magnetostrictive element arranged to receive the acoustic wave, and a readout circuit to detect one of either a change in the magnetostrictive element or a change in the acoustic wave.Type: GrantFiled: December 11, 2017Date of Patent: December 5, 2023Assignee: THE REGENTS OF THE UNIVERSITY OF CALIFORNIAInventors: Sayeef Salahuddin, Dominic E. Labanowski
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Patent number: 11740192Abstract: A system and method for design and operation an acoustically driven ferromagnetic resonance (ADFMR) based sensor for measuring electromagnetic fields that includes: a power source providing an electrical signal to an ADFMR circuit, sensitive to electromagnetic fields, wherein the ADFMR circuit comprises an ADFMR device. The system detect and measure external electromagnetic (EM) fields by measuring a perturbation of the electrical signal through the ADFMR circuit due to the EM fields. The system and method may function to facilitate the design and operation of a chip-scale ADFMR device usable to measure EM fields.Type: GrantFiled: December 14, 2020Date of Patent: August 29, 2023Assignee: Sonera Magnetics, Inc.Inventors: Dominic Labanowski, Sayeef Salahuddin
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Patent number: 11742011Abstract: The present disclosure relates to a magnetic memory structure with a voltage-controlled gain-cell configuration, which includes a memory resistive device, a first transistor connected in series with the memory resistive device, and a second transistor. The memory resistive device has a baseline resistance larger than 10 M?, and is eligible to exhibit a ‘1’ state and a ‘0’ state and exhibit a resistance change between the ‘1’ state and the ‘0’ state. The second transistor has a gate connected to a connection node of the first transistor and the memory resistive device. When the memory resistive device exhibits the ‘1’ state, a gate voltage for the second transistor is smaller than a threshold voltage of the second transistor, and when the memory resistive device exhibits the ‘0’ state, the gate voltage for the second transistor is larger than the threshold voltage of the second transistor.Type: GrantFiled: August 11, 2021Date of Patent: August 29, 2023Assignee: The Regents of the University of CaliforniaInventors: Sayeef Salahuddin, Shehrin Sayed
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Publication number: 20230260969Abstract: An electronic device with embedded access to a high-bandwidth, high-capacity fast-access memory includes (a) a memory circuit fabricated on a first semiconductor die, wherein the memory circuit includes numerous modular memory units, each modular memory unit having (i) a three-dimensional array of storage transistors, and (ii) a group of conductors exposed to a surface of the first semiconductor die, the group of conductors being configured for communicating control, address and data signals associated the memory unit; and (b) a logic circuit fabricated on a second semiconductor die, wherein the logic circuit also includes conductors each exposed at a surface of the second semiconductor die, wherein the first and second semiconductor dies are wafer-bonded, such that the conductors exposed at the surface of the first semiconductor die are each electrically connected to a corresponding one of the conductors exposed to the surface of the second semiconductor die.Type: ApplicationFiled: April 24, 2023Publication date: August 17, 2023Inventors: Khandker Nazrul Quader, Robert Norman, Frank Sai-keung Lee, Christopher J. Petti, Scott Brad Herner, Siu Lung Chan, Sayeef Salahuddin, Mehrdad Mofidi, Eli Harari
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Publication number: 20230259283Abstract: A first circuit formed on a first semiconductor substrate is wafer-bonded to a second circuit formed on a second memory circuit, wherein the first circuit includes quasi-volatile or non-volatile memory circuits and wherein the second memory circuit includes fast memory circuits that have lower read latencies than the quasi-volatile or non-volatile memory circuits, as well as logic circuits. The volatile and non-volatile memory circuits may include static random-access memory (SRAM) circuits, dynamic random-access memory (DRAM) circuits, embedded DRAM (eDRAM) circuits, magnetic random-access memory (MRAM) circuits, embedded MRAM (eMRAM), or any suitable combination of these circuits.Type: ApplicationFiled: April 24, 2023Publication date: August 17, 2023Inventors: Youn Cheul Kim, Richard S. Chernicoff, Khandker Nazrul Quader, Robert D. Norman, Tianhong Yan, Sayeef Salahuddin, Eli Harari
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Patent number: 11675500Abstract: A first circuit formed on a first semiconductor substrate is wafer-bonded to a second circuit formed on a second memory circuit, wherein the first circuit includes quasi-volatile or non-volatile memory circuits and wherein the second memory circuit includes fast memory circuits that have lower read latencies than the quasi-volatile or non-volatile memory circuits, as well as logic circuits. The volatile and non-volatile memory circuits may include static random-access memory (SRAM) circuits, dynamic random-access memory (DRAM) circuits, embedded DRAM (eDRAM) circuits, magnetic random-access memory (MRAM) circuits, embedded MRAM (eMRAM), or any suitable combination of these circuits.Type: GrantFiled: February 5, 2021Date of Patent: June 13, 2023Assignee: SUNRISE MEMORY CORPORATIONInventors: Youn Cheul Kim, Richard S. Chernicoff, Khandker Nazrul Quader, Robert D. Norman, Tianhong Yan, Sayeef Salahuddin, Eli Harari
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Patent number: 11670620Abstract: An electronic device with embedded access to a high-bandwidth, high-capacity fast-access memory includes (a) a memory circuit fabricated on a first semiconductor die, wherein the memory circuit includes numerous modular memory units, each modular memory unit having (i) a three-dimensional array of storage transistors, and (ii) a group of conductors exposed to a surface of the first semiconductor die, the group of conductors being configured for communicating control, address and data signals associated the memory unit; and (b) a logic circuit fabricated on a second semiconductor die, wherein the logic circuit also includes conductors each exposed at a surface of the second semiconductor die, wherein the first and second semiconductor dies are wafer-bonded, such that the conductors exposed at the surface of the first semiconductor die are each electrically connected to a corresponding one of the conductors exposed to the surface of the second semiconductor die.Type: GrantFiled: January 29, 2020Date of Patent: June 6, 2023Assignee: SUNRISE MEMORY CORPORATIONInventors: Khandker Nazrul Quader, Robert Norman, Frank Sai-keung Lee, Christopher J. Petti, Scott Brad Herner, Siu Lung Chan, Sayeef Salahuddin, Mehrdad Mofidi, Eli Harari
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Publication number: 20230065451Abstract: A storage transistor has a tunnel dielectric layer and a charge-trapping layer between a channel region and a gate electrode, wherein the charge-tapping layer has a conduction band offset that is less than the lowering of the tunneling barrier in the tunnel dielectric layer when a programming voltage is applied, such that electrons direct tunnel into the charge-trapping layer. The conduction band of the charge-trapping layer has a value between ?1.0 eV and 2.3 eV. The storage transistor may further include a barrier layer between the tunnel dielectric layer and the charge-trapping layer, the barrier layer having a conduction band offset less than the conduction band offset of the charge-trapping layer.Type: ApplicationFiled: October 13, 2022Publication date: March 2, 2023Inventors: Sayeef Salahuddin, George Samachisa, Wu-Yi Henry Chien, Eli Harari
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Publication number: 20230045804Abstract: The present disclosure relates to a magnetic memory structure with a voltage-controlled gain-cell configuration, which includes a memory resistive device, a first transistor connected in series with the memory resistive device, and a second transistor. The memory resistive device has a baseline resistance larger than 10 M?, and is eligible to exhibit a ‘1’ state and a ‘0’ state and exhibit a resistance change between the ‘1’ state and the ‘0’ state. The second transistor has a gate connected to a connection node of the first transistor and the memory resistive device. When the memory resistive device exhibits the ‘1’ state, a gate voltage for the second transistor is smaller than a threshold voltage of the second transistor, and when the memory resistive device exhibits the ‘0’ state, the gate voltage for the second transistor is larger than the threshold voltage of the second transistor.Type: ApplicationFiled: August 11, 2021Publication date: February 16, 2023Inventors: Sayeef Salahuddin, Shehrin Sayed
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Patent number: 11515432Abstract: A storage transistor has a tunnel dielectric layer and a charge-trapping layer between a channel region and a gate electrode, wherein the charge-tapping layer has a conduction band offset that is less than the lowering of the tunneling barrier in the tunnel dielectric layer when a programming voltage is applied, such that electrons direct tunnel into the charge-trapping layer. The conduction band of the charge-trapping layer is has a value between ?1.0 eV and 2.3 eV. The storage transistor may further include a barrier layer between the tunnel dielectric layer and the charge-trapping layer, the barrier layer having a conduction band offset less than the conduction band offset of the charge-trapping layer.Type: GrantFiled: January 22, 2021Date of Patent: November 29, 2022Assignee: SUNRISE MEMORY CORPORATIONInventors: Sayeef Salahuddin, George Samachisa, Wu-Yi Henry Chien, Eli Harari
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Patent number: 11488676Abstract: NOR memory strings may be used for implementations of logic functions involving many Boolean variables, or to generate analog signals whose magnitudes are each representative of the bit values of many Boolean variables. The advantage of using NOR memory strings in these manners is that the logic function or analog signal generation may be accomplished within one simultaneous read operation on the NOR memory strings.Type: GrantFiled: August 5, 2021Date of Patent: November 1, 2022Assignee: SUNRISE MEMORY CORPORATIONInventors: Sayeef Salahuddin, Robert D. Norman, Eli Harari
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Publication number: 20210398949Abstract: An electronic device with embedded access to a high-bandwidth, high-capacity fast-access memory includes (a) a memory circuit fabricated on a first semiconductor die, wherein the memory circuit includes numerous modular memory units, each modular memory unit having (i) a three-dimensional array of storage transistors, and (ii) a group of conductors exposed to a surface of the first semiconductor die, the group of conductors being configured for communicating control, address and data signals associated the memory unit; and (b) a logic circuit fabricated on a second semiconductor die, wherein the logic circuit also includes conductors each exposed at a surface of the second semiconductor die, wherein the first and second semiconductor dies are wafer-bonded, such that the conductors exposed at the surface of the first semiconductor die are each electrically connected to a corresponding one of the conductors exposed to the surface of the second semiconductor die.Type: ApplicationFiled: September 3, 2021Publication date: December 23, 2021Inventors: Khandker Nazrul Quader, Robert Norman, Frank Sai-keung Lee, Christopher J. Petti, Scott Brad Herner, Siu Lung Chan, Sayeef Salahuddin, Mehrdad Mofidi, Eli Harari
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Publication number: 20210366560Abstract: NOR memory strings may be used for implementations of logic functions involving many Boolean variables, or to generate analog signals whose magnitudes are each representative of the bit values of many Boolean variables. The advantage of using NOR memory strings in these manners is that the logic function or analog signal generation may be accomplished within one simultaneous read operation on the NOR memory strings.Type: ApplicationFiled: August 5, 2021Publication date: November 25, 2021Inventors: Sayeef Salahuddin, Robert D. Normal, Eli Harari
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Patent number: 11120884Abstract: NOR memory strings may be used for implementations of logic functions involving many Boolean variables, or to generate analog signals whose magnitudes are each representative of the bit values of many Boolean variables. The advantage of using NOR memory strings in these manners is that the logic function or analog signal generation may be accomplished within one simultaneous read operation on the NOR memory strings.Type: GrantFiled: January 15, 2020Date of Patent: September 14, 2021Assignee: SUNRISE MEMORY CORPORATIONInventors: Sayeef Salahuddin, Robert D. Normal, Eli Harari
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Publication number: 20210247910Abstract: A first circuit formed on a first semiconductor substrate is wafer-bonded to a second circuit formed on a second memory circuit, wherein the first circuit includes quasi-volatile or non-volatile memory circuits and wherein the second memory circuit includes fast memory circuits that have lower read latencies than the quasi-volatile or non-volatile memory circuits, as well as logic circuits. The volatile and non-volatile memory circuits may include static random-access memory (SRAM) circuits, dynamic random-access memory (DRAM) circuits, embedded DRAM (eDRAM) circuits, magnetic random-access memory (MRAM) circuits, embedded MRAM (eMRAM), or any suitable combination of these circuits.Type: ApplicationFiled: February 5, 2021Publication date: August 12, 2021Inventors: Youn Cheul Kim, Richard S. Chernicoff, Khandker Nazrul Quader, Robert D. Norman, Tianhong Yan, Sayeef Salahuddin, Eli Harari
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Publication number: 20210226071Abstract: A storage transistor has a tunnel dielectric layer and a charge-trapping layer between a channel region and a gate electrode, wherein the charge-tapping layer has a conduction band offset that is less than the lowering of the tunneling barrier in the tunnel dielectric layer when a programming voltage is applied, such that electrons direct tunnel into the charge-trapping layer. The conduction band of the charge-trapping layer is has a value between ?1.0 eV and 2.3 eV. The storage transistor may further include a barrier layer between the tunnel dielectric layer and the charge-trapping layer, the barrier layer having a conduction band offset less than the conduction band offset of the charge-trapping layer.Type: ApplicationFiled: January 22, 2021Publication date: July 22, 2021Inventors: Sayeef Salahuddin, George Samachisa, Wu-Yi Henry Chien, Eli Harari
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Publication number: 20210181132Abstract: A system and method for an acoustically driven ferromagnetic resonance (ADFMR) based sensor including: a power source, that provides an electrical signal to power the system; and an ADFMR circuit, sensitive to electromagnetic fields, wherein the ADFMR circuit comprises an ADFMR device. The system functions to detect and measure external electromagnetic (EM) fields by measuring a perturbation of the electrical signal through the ADFMR circuit due to the EM fields.Type: ApplicationFiled: December 14, 2020Publication date: June 17, 2021Inventors: Dominic Labanowski, Sayeef Salahuddin