Abstract: A parallel architecture for combinatorial optimization can be implemented on a parallel processor, such as a field programmable gate array (FPGA), that includes a memory management system coupled to a memory of the parallel processor, wherein the memory stores a weight matrix; a sampling engine on the parallel processor, the sampling engine coupled to receive weights of the weight matrix stored in the memory from the memory management system and perform as a restricted Boltzmann machine for a set of inputs using the received weights, wherein the sampling engine comprises a dual architecture of a first circuit for updating visible states and a second circuit for updating hidden states; and a probability estimator that receives updated visible states and updated hidden states from the sampling engine.

Abstract: A storage transistor has a tunnel dielectric layer and a charge-trapping layer between a channel region and a gate electrode, wherein the charge-tapping layer has a conduction band offset that is less than the lowering of the tunneling barrier in the tunnel dielectric layer when a programming voltage is applied, such that electrons direct tunnel into the charge-trapping layer. The conduction band of the charge-trapping layer has a value between ?1.0 eV and 2.3 eV. The storage transistor may further include a barrier layer between the tunnel dielectric layer and the charge-trapping layer, the barrier layer having a conduction band offset less than the conduction band offset of the charge-trapping layer.

Abstract: An electronic device with embedded access to a high-bandwidth, high-capacity fast-access memory includes (a) a memory circuit fabricated on a first semiconductor die, wherein the memory circuit includes numerous modular memory its, each modular memory unit having (i) a three-dimensional array of storage transistors, and (ii) a group of conductors exposed to a surface of the first semiconductor die, the group of conductors being configured for communicating control, address and data signals associated the memory unit; and (b) a logic circuit fabricated on a second semiconductor die, wherein the logic circuit also includes conductors each exposed at a surface of the second semiconductor die, wherein the first and second semiconductor dies are wafer-bonded, such that the conductors exposed at the surface of the first semiconductor die are each electrically connected to a corresponding one of the conductors exposed to the surface of the second semiconductor die.

Abstract: A first circuit formed on a first semiconductor substrate is wafer-bonded to a second circuit formed on a second memory circuit, wherein the first circuit includes quasi-volatile or non-volatile memory circuits and wherein the second memory circuit includes fast memory circuits that have lower read latencies than the quasi-volatile or non-volatile memory circuits, as well as logic circuits. The volatile and non-volatile memory circuits may include static random-access memory (SRAM) circuits, dynamic random-access memory (DRAM) circuits, embedded DRAM (eDRAM) circuits, magnetic random-access memory (MRAM) circuits, embedded MRAM (eMRAM), or any suitable combination of these circuits.

Abstract: A rectifier device, has a Hall layer comprising a layer of a Hall material, and a spin-orbit layer adjacent the Hall layer. The spin-orbit layer has a spin-orbit material having a first surface and a second surface, a ferromagnet adjacent the spin-orbit material, and oxide on the outer surfaces of the spin-orbit layer. A rectifying system has an array of the above rectifying devices having a number, K, of parallel branches, each branch having N devices, branch electrical connections between corresponding devices in each of the parallel branches, and device electrical connection between devices in each parallel branch.

Abstract: A first circuit formed on a first semiconductor substrate is wafer-bonded to a second circuit formed on a second memory circuit, wherein the first circuit includes quasi-volatile or non-volatile memory circuits and wherein the second memory circuit includes fast memory circuits that have lower read latencies than the quasi-volatile or non-volatile memory circuits, as well as logic circuits. The volatile and non-volatile memory circuits may include static random-access memory (SRAM) circuits, dynamic random-access memory (DRAM) circuits, embedded DRAM (eDRAM) circuits, magnetic random-access memory (MRAM) circuits, embedded MRAM (eMRAM), or any suitable combination of these circuits.

Abstract: An electronic device with embedded access to a high-bandwidth, high-capacity fast-access memory includes (a) a memory circuit fabricated on a first semiconductor die, wherein the memory circuit includes numerous modular memory units, each modular memory unit having (i) a three-dimensional array of storage transistors, and (ii) a group of conductors exposed to a surface of the first semiconductor die, the group of conductors being configured for communicating control, address and data signals associated the memory unit; and (b) a logic circuit fabricated on a second semiconductor die, wherein the logic circuit also includes conductors each exposed at a surface of the second semiconductor die, wherein the first and second semiconductor dies are wafer-bonded, such that the conductors exposed at the surface of the first semiconductor die are each electrically connected to a corresponding one of the conductors exposed to the surface of the second semiconductor die.

Abstract: A ferroelectric field-effect transistor having an endurance exceeding 1012 cycles is disclosed. The ferroelectric field-effect transistor includes a substrate, a source disposed over a first region of the semiconductor substrate, a drain disposed over a second region of the substrate, wherein the second region is spaced apart from the first region. The ferroelectric field-effect transistor includes a channel made of a semiconductor material within a third region of the substrate that is between the first region and the second region. The ferroelectric field-effect transistor further includes a gate stack having an interfacial layer disposed over the channel, wherein the interfacial layer has a permittivity that is greater than 3.9, and a layer of ferroelectric material disposed over the interfacial layer.

Abstract: Disclosed are HfO2—ZrO2 superlattice heterostructures such as a gate stack (24), stabilized with mixed ferroelectric-antiferroelectric order. directly integrated onto silicon (Si) transistors and scaled down to ˜20 ?. the same gate oxide thickness required for high-performance transistors. The overall equivalent oxide thickness in metal-oxide-semiconductor capacitors is ˜6.5 ? effective SiO2 thickness, which is even smaller than the interfacial SiO2 thickness (8.0-8.5 ?) itself. and the resulting large capacitance cannot be achieved in conventional HfO2-based high-? dielectric gate stacks without scavenging the interfacial SiO2. which has adverse effects on the electron transport and gate leakage current. Accordingly. the disclosed gate stacks (24), which do not require such scavenging.

Abstract: A system and method for an acoustically driven ferromagnetic resonance (ADFMR) based sensor including: a power source, that provides an electrical signal to power the system; and an ADFMR circuit, sensitive to electromagnetic fields, wherein the ADFMR circuit comprises an ADFMR device. The system functions to detect and measure external electromagnetic (EM) fields by measuring a perturbation of the electrical signal through the ADFMR circuit due to the EM fields.

Abstract: A ferroelectric field-effect transistor having an endurance exceeding 1012 cycles is disclosed. The ferroelectric field-effect transistor includes a substrate, a source disposed over a first region of the semiconductor substrate, a drain disposed over a second region of the substrate, wherein the second region is spaced apart from the first region. The ferroelectric field-effect transistor includes a channel made of a semiconductor material within a third region of the substrate that is between the first region and the second region. The ferroelectric field-effect transistor further includes a gate stack having an interfacial layer disposed over the channel, wherein the interfacial layer has a permittivity that is greater than 3.9, and a layer of ferroelectric material disposed over the interfacial layer.

Abstract: An electronic device with embedded access to a high-bandwidth, high-capacity fast-access memory includes (a) a memory circuit fabricated on a first semiconductor die, wherein the memory circuit includes numerous modular memory units, each modular memory unit having (i) a three-dimensional array of storage transistors, and (ii) a group of conductors exposed to a surface of the first semiconductor die, the group of conductors being configured for communicating control, address and data signals associated the memory unit; and (b) a logic circuit fabricated on a second semiconductor die, wherein the logic circuit also includes conductors each exposed at a surface of the second semiconductor die, wherein the first and second semiconductor dies are wafer-bonded, such that the conductors exposed at the surface of the first semiconductor die are each electrically connected to a corresponding one of the conductors exposed to the surface of the second semiconductor die.

Abstract: An acoustically driven ferromagnetic resonance (ADFMR) device has a piezoelectric element comprised of piezoelectric material, first and second electrodes arranged in a vertical stack with the piezoelectric element to activate the piezoelectric element to generate an acoustic wave, a radio frequency voltage source electrically connected to the first electrode, a magnet comprised of a magnetostrictive material in the vertical stack with the first and second electrodes and the piezoelectric element to receive the acoustic wave, wherein the acoustic wave resonates at a ferromagnetic resonance of the magnetostrictive material, and a readout circuit to detect a change in the acoustic wave by detecting one of an output voltage amplitude, a change in impedance or a reflection of the acoustic wave in the magnet to measure an unknown magnetic field in which the ADFMR device resides and as experienced at the magnetostrictive element.

Abstract: An acoustically driven ferromagnetic resonance (ADFMR) device includes a piezoelectric element, a pair of transducers arranged to activate the piezoelectric element to generate an acoustic wave, a magnetostrictive element arranged to receive the acoustic wave, and a readout circuit to detect one of either a change in the magnetostrictive element or a change in the acoustic wave.

Abstract: The present disclosure relates to a magnetic memory structure with a voltage-controlled gain-cell configuration, which includes a memory resistive device, a first transistor connected in series with the memory resistive device, and a second transistor. The memory resistive device has a baseline resistance larger than 10 M?, and is eligible to exhibit a ‘1’ state and a ‘0’ state and exhibit a resistance change between the ‘1’ state and the ‘0’ state. The second transistor has a gate connected to a connection node of the first transistor and the memory resistive device. When the memory resistive device exhibits the ‘1’ state, a gate voltage for the second transistor is smaller than a threshold voltage of the second transistor, and when the memory resistive device exhibits the ‘0’ state, the gate voltage for the second transistor is larger than the threshold voltage of the second transistor.

Abstract: A system and method for design and operation an acoustically driven ferromagnetic resonance (ADFMR) based sensor for measuring electromagnetic fields that includes: a power source providing an electrical signal to an ADFMR circuit, sensitive to electromagnetic fields, wherein the ADFMR circuit comprises an ADFMR device. The system detect and measure external electromagnetic (EM) fields by measuring a perturbation of the electrical signal through the ADFMR circuit due to the EM fields. The system and method may function to facilitate the design and operation of a chip-scale ADFMR device usable to measure EM fields.

Abstract: A first circuit formed on a first semiconductor substrate is wafer-bonded to a second circuit formed on a second memory circuit, wherein the first circuit includes quasi-volatile or non-volatile memory circuits and wherein the second memory circuit includes fast memory circuits that have lower read latencies than the quasi-volatile or non-volatile memory circuits, as well as logic circuits. The volatile and non-volatile memory circuits may include static random-access memory (SRAM) circuits, dynamic random-access memory (DRAM) circuits, embedded DRAM (eDRAM) circuits, magnetic random-access memory (MRAM) circuits, embedded MRAM (eMRAM), or any suitable combination of these circuits.

Abstract: An electronic device with embedded access to a high-bandwidth, high-capacity fast-access memory includes (a) a memory circuit fabricated on a first semiconductor die, wherein the memory circuit includes numerous modular memory units, each modular memory unit having (i) a three-dimensional array of storage transistors, and (ii) a group of conductors exposed to a surface of the first semiconductor die, the group of conductors being configured for communicating control, address and data signals associated the memory unit; and (b) a logic circuit fabricated on a second semiconductor die, wherein the logic circuit also includes conductors each exposed at a surface of the second semiconductor die, wherein the first and second semiconductor dies are wafer-bonded, such that the conductors exposed at the surface of the first semiconductor die are each electrically connected to a corresponding one of the conductors exposed to the surface of the second semiconductor die.

Abstract: A first circuit formed on a first semiconductor substrate is wafer-bonded to a second circuit formed on a second memory circuit, wherein the first circuit includes quasi-volatile or non-volatile memory circuits and wherein the second memory circuit includes fast memory circuits that have lower read latencies than the quasi-volatile or non-volatile memory circuits, as well as logic circuits. The volatile and non-volatile memory circuits may include static random-access memory (SRAM) circuits, dynamic random-access memory (DRAM) circuits, embedded DRAM (eDRAM) circuits, magnetic random-access memory (MRAM) circuits, embedded MRAM (eMRAM), or any suitable combination of these circuits.

Abstract: An electronic device with embedded access to a high-bandwidth, high-capacity fast-access memory includes (a) a memory circuit fabricated on a first semiconductor die, wherein the memory circuit includes numerous modular memory units, each modular memory unit having (i) a three-dimensional array of storage transistors, and (ii) a group of conductors exposed to a surface of the first semiconductor die, the group of conductors being configured for communicating control, address and data signals associated the memory unit; and (b) a logic circuit fabricated on a second semiconductor die, wherein the logic circuit also includes conductors each exposed at a surface of the second semiconductor die, wherein the first and second semiconductor dies are wafer-bonded, such that the conductors exposed at the surface of the first semiconductor die are each electrically connected to a corresponding one of the conductors exposed to the surface of the second semiconductor die.