Abstract: A system includes a storage system and circuitry coupled to the storage system. The circuitry is configured to perform operations comprising determining a type of a received data packet, determining a destination of the received data packet, and determining whether the received data packet is of a particular type or has a particular destination. The operations further comprise, responsive to determining that the received data packet is of the particular type or has the particular destination, rerouting the received data packet from the particular destination to a register of the storage system.

Abstract: An example memory sub-system includes a memory device and a processing device, operatively coupled to the memory device. The processing device is configured to receive a memory access request specifying a logical address of a data item and a memory access operation to be performed with respect to the data item; produce a truncated logical address by applying a predefined mathematical transformation to the specified logical address; identifying, in an address translation table, an address translation table entry identified by the truncated logical address; and perform the memory access operation using a physical address specified by the address translation table entry.

Abstract: Implementations described herein relate to memory device log data storage. In some implementations, a memory device may store a first data stream associated with a first type of log data in a circular buffer. The memory device may store a second data stream associated with a second type of log data in another memory location. The memory device may detect an event included in the second data stream that is associated with an attribute level that satisfies a threshold. The memory device may write data stored in the circular buffer after a time at which the event is detected to a non-volatile memory based on the attribute level satisfying the threshold, wherein the data stored in the circular buffer is stored in the non-volatile memory in connection with data associated with the event.

Abstract: In some implementations, a memory device may receive, from a host device, a read command indicating data and one or more logical block addresses to be read from a memory of the memory device. The memory device may obtain a memory unit from the memory based on the read command. The memory device may determine status information associated with the one or more logical block addresses based on information indicated by the memory unit. The memory device may generate a single data transfer request associated with the one or more logical block addresses, where the single data transfer request indicates status indicators associated with respective logical block addresses of the one or more logical block addresses. The memory device may provide, to the host device, one or more responses to the read command, where the one or more responses are based on the status indicators.

Abstract: Implementations described herein relate to memory device operations for unaligned write operations. In some implementations, a memory device may receive, from a host device, a write command indicating data having a first size that corresponds to a first write unit and a first logical address. The memory device may allocate a set of buffers for the write command. The memory device may determine a set of physical addresses corresponding to a physical address that is associated with the second size, where the set of physical addresses are each associated with the first size. The memory device may merge stored data from the set of physical addresses to one or more buffers, from the set of buffers, that do not include the data to generate a data unit having the second size. The memory device may write the data unit to memory indicated by the set of physical addresses.

Abstract: Methods, systems, and devices for command batching for a memory sub-system are described. A memory sub-system can receive a plurality of commands for a plurality of transfer units of a memory sub-system and generate a list of the plurality of transfer units that includes pointers between the plurality of transfer units. The memory sub-system can store at least one pointer of the list in a shared memory that is shared by a plurality of cores, the at least one pointer indicating a next transfer unit of the list. The memory sub-system can send an indicator of a first transfer unit of the list based on storing the at least one pointer in the shared memory and retrieve the plurality of transfer units from the shared memory based on sending the indicator of the first transfer unit and storing the at least one pointer in the shared memory.

Abstract: A write command is received, for example, from a host system, which operates on a first logical address range. A read command is received that specifies a second logical address range that matches the first logical address range. Responsive to determining that a deallocate command has been received after the write command, zero-filled data is returned in response to the read command.

Abstract: Methods, systems, and devices for the dynamic selection of cores for processing responses are described. A memory sub-system can receive, from a host system, a read command to retrieve data. The memory sub-system can include a first core and a second core. The first core can process the read command based on receiving the read command. The first core can identify the second core for processing a read response associated with the read command. The first core can issue an internal command to retrieve the data from a memory device of the memory sub-system. The internal command can include an indication of the second core selected to process the read response.

Abstract: A system includes a storage system and circuitry coupled to the storage system. The circuitry is configured to perform operations comprising determining a type of a received data packet, determining a destination of the received data packet, and determining whether the received data packet is of a particular type or has a particular destination. The operations further comprise, responsive to determining that the received data packet is of the particular type or has the particular destination, rerouting the received data packet from the particular destination to a register of the storage system.

Abstract: Methods, systems, and devices for command batching for a memory sub-system are described. A memory sub-system can receive a plurality of commands for a plurality of transfer units of a memory sub-system and generate a list of the plurality of transfer units that includes pointers between the plurality of transfer units. The memory sub-system can store at least one pointer of the list in a shared memory that is shared by a plurality of cores, the at least one pointer indicating a next transfer unit of the list. The memory sub-system can send an indicator of a first transfer unit of the list based on storing the at least one pointer in the shared memory and retrieve the plurality of transfer units from the shared memory based on sending the indicator of the first transfer unit and storing the at least one pointer in the shared memory.

Abstract: A system includes a storage system and circuitry coupled to the storage system. The circuitry is configured to perform operations comprising determining a type of a received data packet, determining a destination of the received data packet, and determining whether the received data packet is of a particular type or has a particular destination. The operations further comprise, responsive to determining that the received data packet is of the particular type or has the particular destination, rerouting the received data packet from the particular destination to a register of the storage system.

Abstract: Methods, systems, and devices for command batching for a memory sub-system are described. A memory sub-system can receive a plurality of commands for a plurality of transfer units of a memory sub-system and generate a list of the plurality of transfer units that includes pointers between the plurality of transfer units. The memory sub-system can store at least one pointer of the list in a shared memory that is shared by a plurality of cores, the at least one pointer indicating a next transfer unit of the list. The memory sub-system can send an indicator of a first transfer unit of the list based on storing the at least one pointer in the shared memory and retrieve the plurality of transfer units from the shared memory based on sending the indicator of the first transfer unit and storing the at least one pointer in the shared memory.

Abstract: A system includes a storage system and circuitry coupled to the storage system. The circuitry is configured to perform operations comprising determining a type of a received data packet, determining a destination of the received data packet, and determining whether the received data packet is of a particular type or has a particular destination. The operations further comprise, responsive to determining that the received data packet is of the particular type or has the particular destination, rerouting the received data packet from the particular destination to a register of the storage system.

Abstract: A system includes a storage system and circuitry coupled to the storage system. The circuitry is configured to perform operations comprising attempting a communication of a first completion associated with a first transaction processed by the storage system. The operations further comprise, responsive to failure of the communication of the first completion, storing the first completion in a local memory of the storage system and subsequently attempting a communication of the first completion from the local memory.

Abstract: Methods, systems, and devices for sequential prefetching through a linking array are described. A prefetch manager can detect that a set of tags occupying a queue of a memory sub-system corresponds to a single read descriptor indicating a sequential read pattern. The prefetch manager can determine that a number of the set of tags occupying the queue is below a queue threshold and store data associated with at least one tag of the set of tags in an internal performance memory of the memory sub-system based on the detecting and the determining. In such cases, the prefetch manager can prefetch data from a memory manager and store in the internal performance memory.

Abstract: Methods, systems, and devices for the dynamic selection of cores for processing responses are described. A memory sub-system can receive, from a host system, a read command to retrieve data. The memory sub-system can include a first core and a second core. The first core can process the read command based on receiving the read command. The first core can identify the second core for processing a read response associated with the read command. The first core can issue an internal command to retrieve the data from a memory device of the memory sub-system. The internal command can include an indication of the second core selected to process the read response.

Abstract: Methods, systems, and devices for command batching for a memory sub-system are described. A memory sub-system can receive a plurality of commands for a plurality of transfer units of a memory sub-system and generate a list of the plurality of transfer units that includes pointers between the plurality of transfer units. The memory sub-system can store at least one pointer of the list in a shared memory that is shared by a plurality of cores, the at least one pointer indicating a next transfer unit of the list. The memory sub-system can send an indicator of a first transfer unit of the list based on storing the at least one pointer in the shared memory and retrieve the plurality of transfer units from the shared memory based on sending the indicator of the first transfer unit and storing the at least one pointer in the shared memory.

Abstract: A write command is received, for example, from a host system, which operates on a first logical address range. A read command is received that specifies a second logical address range that matches the first logical address range. Responsive to determining that a deallocate command has been received after the write command, zero-filled data is returned in response to the read command.

Abstract: Methods, systems, and devices for linking access commands for a memory sub-system of a memory sub-system are described. A first write command that includes first data can be received. The first write command can be associated with a first identifier. An internal read command to retrieve data stored in the transfer unit of the memory sub-system can be issued based on receiving the first write command. A second write command that includes second data can be received. The second write command can be associated with a second identifier. The first and second identifiers can be linked based on receiving the second write command and an internal write command that includes the first data associated with the first write command and the second data associated with the second write command can be issued.

Abstract: A read command is received from a host system, which operates on a first logical block address (LBA) range that at least partially overlaps with a second LBA range associated with a write command. A state associated with the write command is determined, where the state is indicative of whether a logical-to-physical (L2P) mapping table has been updated based on the write command. Data corresponding to the first LBA range is transmitted to the host system based on the state associated with the write command.