Patents by Inventor Scheheresade Virani

Scheheresade Virani has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11099785
    Abstract: Methods, systems, and devices for linking access commands for a memory sub-system of a memory sub-system are described. A first write command that includes first data can be received. The first write command can be associated with a first identifier. An internal read command to retrieve data stored in the transfer unit of the memory sub-system can be issued based on receiving the first write command. A second write command that includes second data can be received. The second write command can be associated with a second identifier. The first and second identifiers can be linked based on receiving the second write command and an internal write command that includes the first data associated with the first write command and the second data associated with the second write command can be issued.
    Type: Grant
    Filed: December 23, 2019
    Date of Patent: August 24, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Ning Zhao, Yun Li, Scheheresade Virani, Zachary Andrew Pete Vogel
  • Publication number: 20210191870
    Abstract: A read command is received from a host system, which operates on a first logical block address (LBA) range that at least partially overlaps with a second LBA range associated with a write command. A state associated with the write command is determined, where the state is indicative of whether a logical-to-physical (L2P) mapping table has been updated based on the write command. Data corresponding to the first LBA range is transmitted to the host system based on the state associated with the write command.
    Type: Application
    Filed: December 19, 2019
    Publication date: June 24, 2021
    Inventors: Scheheresade Virani, Byron D. Harris
  • Publication number: 20210191652
    Abstract: Methods, systems, and devices for linking access commands for a memory sub-system of a memory sub-system are described. A first write command that includes first data can be received. The first write command can be associated with a first identifier. An internal read command to retrieve data stored in the transfer unit of the memory sub-system can be issued based on receiving the first write command. A second write command that includes second data can be received. The second write command can be associated with a second identifier. The first and second identifiers can be linked based on receiving the second write command and an internal write command that includes the first data associated with the first write command and the second data associated with the second write command can be issued.
    Type: Application
    Filed: December 23, 2019
    Publication date: June 24, 2021
    Inventors: Ning Zhao, Yun Li, Scheheresade Virani, Zachary Andrew Pete Vogel
  • Patent number: 11042481
    Abstract: A read command is received from a host system, which operates on a first logical block address (LBA) range that at least partially overlaps with a second LBA range associated with a write command. A state associated with the write command is determined, where the state is indicative of whether a logical-to-physical (L2P) mapping table has been updated based on the write command. Data corresponding to the first LBA range is transmitted to the host system based on the state associated with the write command.
    Type: Grant
    Filed: December 19, 2019
    Date of Patent: June 22, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Scheheresade Virani, Byron D. Harris
  • Patent number: 10564853
    Abstract: Systems and methods for determining locality of an incoming command relative to previously identified write or read streams is disclosed. NVM Express (NVMe) implements a paired submission queue and completion queue mechanism, with host software on the host device placing commands into multiple submission queues. The memory device fetches the commands from the multiple submission queues, which results in the incoming commands being interspersed. In order to determine whether the incoming commands should be assigned to previously identified read or write streams, the locality of the incoming commands relative to the previously identified read or write streams is analyzed. One example of locality is proximity in address space. In response to determining locality, the incoming commands are assigned to the various streams.
    Type: Grant
    Filed: April 26, 2017
    Date of Patent: February 18, 2020
    Assignee: Western Digital Technologies, Inc.
    Inventors: Vitali Linkovsky, Shay Benisty, William Guthrie, Scheheresade Virani
  • Publication number: 20180314421
    Abstract: Systems and methods for determining locality of an incoming command relative to previously identified write or read streams is disclosed. NVM Express (NVMe) implements a paired submission queue and completion queue mechanism, with host software on the host device placing commands into multiple submission queues. The memory device fetches the commands from the multiple submission queues, which results in the incoming commands being interspersed. In order to determine whether the incoming commands should be assigned to previously identified read or write streams, the locality of the incoming commands relative to the previously identified read or write streams is analyzed. One example of locality is proximity in address space. In response to determining locality, the incoming commands are assigned to the various streams.
    Type: Application
    Filed: April 26, 2017
    Publication date: November 1, 2018
    Applicant: Western Digital Technologies, Inc.
    Inventors: Vitali Linkovsky, Shay Benisty, William Guthrie, Scheheresade Virani