Patents by Inventor Scot H. Rider
Scot H. Rider has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10649511Abstract: A system with a local data collector that collects power management data for a subsystem. The local data collector can determine whether a first formatting associated with a first channel between the local data collector and a system power management data collector is equivalent to a second formatting associated with a second channel between the local data collector and the system power management data collector, and in response to a determination that the first formatting and second formatting are not equivalent format the power management data according to the first formatting; store the power management data formatted according to the first formatting in a first location in a memory; format the power management data according to the second formatting; and store the power management data formatted according to the second formatting in a second location the memory.Type: GrantFiled: April 29, 2019Date of Patent: May 12, 2020Assignee: International Business Machines CorporationInventors: Irving G Baysah, John S Dodson, Karthick Rajamani, Eric E Retter, Scot H Rider, Todd Jon Rosedahl, Gregory Scott Still, Gary Van Huben, Malcolm S Allen-Ware
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Publication number: 20190250682Abstract: A system with a local data collector that collects power management data for a subsystem. The local data collector can determine whether a first formatting associated with a first channel between the local data collector and a system power management data collector is equivalent to a second formatting associated with a second channel between the local data collector and the system power management data collector, and in response to a determination that the first formatting and second formatting are not equivalent format the power management data according to the first formatting; store the power management data formatted according to the first formatting in a first location in a memory; format the power management data according to the second formatting; and store the power management data formatted according to the second formatting in a second location the memory.Type: ApplicationFiled: April 29, 2019Publication date: August 15, 2019Inventors: Irving G. Baysah, John S. Dodson, Karthick Rajamani, Eric E. Retter, Scot H. Rider, Todd Jon Rosedahl, Gregory Scott Still, Gary Van Huben, Malcolm S. Allen-Ware
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Patent number: 10317964Abstract: A system with a local data collector that collects power management data for a subsystem. The local data collector can determine whether a first formatting associated with a first channel between the local data collector and a system power management data collector is equivalent to a second formatting associated with a second channel between the local data collector and the system power management data collector, and in response to a determination that the first formatting and second formatting are not equivalent format the power management data according to the first formatting; store the power management data formatted according to the first formatting in a first location in a memory; format the power management data according to the second formatting; and store the power management data formatted according to the second formatting in a second location the memory.Type: GrantFiled: January 5, 2016Date of Patent: June 11, 2019Assignee: International Business Machines CorporationInventors: Irving G Baysah, John S Dodson, Karthick Rajamani, Eric E Retter, Scot H Rider, Todd Jon Rosedahl, Gregory Scott Still, Gary Van Huben, Malcolm S Allen-Ware
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Patent number: 9477501Abstract: Embodiments relate to a method for encapsulating a hardware application for virtualization. The method surrounds the hardware application with a service layer controller and ring interfaces. The ring interfaces dictates a virtual function that the hardware application is running. The method controls the hardware application so that the hardware application is reset in between each of a plurality of running jobs. The method tags, by the ring interfaces, each of a plurality of requests with an identifier signifying a virtual function that the respective request belongs to. The method ensures that there are not any outstanding requests following a quiesce of the hardware application.Type: GrantFiled: September 30, 2014Date of Patent: October 25, 2016Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Michael J. Cadigan, Jr., Howard M. Haynie, Scot H. Rider, Mushfiq U. Saleheen, Donald W. Schmidt
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Publication number: 20160132085Abstract: A system with a local data collector that collects power management data for a subsystem. The local data collector can determine whether a first formatting associated with a first channel between the local data collector and a system power management data collector is equivalent to a second formatting associated with a second channel between the local data collector and the system power management data collector, and in response to a determination that the first formatting and second formatting are not equivalent format the power management data according to the first formatting; store the power management data formatted according to the first formatting in a first location in a memory; format the power management data according to the second formatting; and store the power management data formatted according to the second formatting in a second location the memory.Type: ApplicationFiled: January 5, 2016Publication date: May 12, 2016Inventors: Irving G. Baysah, John S. Dodson, Karthick Rajamani, Eric E. Retter, Scot H. Rider, Todd Jon Rosedahl, Gregory Scott Still, Gary Van Huben, Malcolm S. Allen-Ware
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Patent number: 9318171Abstract: A computer-system implemented method for dual asynchronous and synchronous memory operation in a memory subsystem includes establishing a synchronous channel between a memory controller and a memory buffer chip. A mode selector determines a reference clock source for a memory domain phase-locked loop of the memory buffer chip based on an operating mode of the memory buffer chip. An output of a nest domain phase-locked loop is provided as the reference clock source to the memory domain phase-locked loop in the memory buffer chip based on the operating mode being synchronous. The nest domain phase-locked loop is operable synchronous to a memory controller phase-locked loop of the memory controller. A separate reference clock is provided independent of the nest domain phase-locked loop as the reference clock to the memory domain phase-locked loop based on the operating mode being asynchronous.Type: GrantFiled: September 30, 2014Date of Patent: April 19, 2016Assignee: International Business Machines CorporationInventors: Gary A. Van Huben, Patrick J. Meaney, John S. Dodson, Scot H. Rider, James C. Gregerson, Eric E. Retter, Irving G. Baysah, Glenn D. Gilda, Lawrence D. Curley, Vesselina K. Papazova
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Patent number: 9298484Abstract: Embodiments relate to a computer system comprising a service layer controller. The computer system comprises a ring interface unit configured to provide access to a host system that enables access to a plurality of virtual machines (VMs). The computer system comprises a hardware application configured to be encapsulated by the service layer controller such that the hardware application communicates to the host system via interfaces controlled by the ring interface unit and service layer controller.Type: GrantFiled: March 14, 2013Date of Patent: March 29, 2016Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Michael J. Cadigan, Jr., Howard M. Haynie, Scot H. Rider, Mushfiq U. Saleheen, Donald W. Schmidt
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Patent number: 9262625Abstract: Embodiments relate an address translation/specification (ATS) field. An aspect includes receiving a work queue entry from a work queue in a main memory by a hardware accelerator, the work queue entry corresponding to an operation of the hardware accelerator that is requested by user-space software, the work queue entry comprising a first ATS field that describes a structure of the work queue entry. Another aspect includes, based on determining that the first ATS field is consistent with the operation corresponding to the work queue entry and the structure of the work queue entry, executing the operation corresponding to the work queue entry by the hardware accelerator. Another aspect includes, based on determining that the first ATS field is not consistent with the operation corresponding to the work queue entry and the structure of the work queue entry, rejecting the work queue entry by the hardware accelerator.Type: GrantFiled: September 30, 2014Date of Patent: February 16, 2016Assignee: International Business Machines CorporationInventors: Frank Haverkamp, Christian Jacobi, Scot H. Rider, Vikramjit Sethi, Randal C. Swanberg, Joerg-Stephan Vogt
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Patent number: 9256729Abstract: Embodiments relate an address translation/specification (ATS) field. An aspect includes receiving a work queue entry from a work queue in a main memory by a hardware accelerator, the work queue entry corresponding to an operation of the hardware accelerator that is requested by user-space software, the work queue entry comprising a first ATS field that describes a structure of the work queue entry. Another aspect includes, based on determining that the first ATS field is consistent with the operation corresponding to the work queue entry and the structure of the work queue entry, executing the operation corresponding to the work queue entry by the hardware accelerator. Another aspect includes, based on determining that the first ATS field is not consistent with the operation corresponding to the work queue entry and the structure of the work queue entry, rejecting the work queue entry by the hardware accelerator.Type: GrantFiled: June 20, 2013Date of Patent: February 9, 2016Assignee: International Business Machines CorporationInventors: Frank Haverkamp, Christian Jacobi, Scot H. Rider, Vikramjit Sethi, Randal C. Swanberg, Joerg-Stephan Vogt
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Patent number: 9250666Abstract: A system with scalable data collection for system management comprises a plurality of local data collectors and a system collector. Each of the local data collectors is coupled with a corresponding subsystem of the system. Each of the local data collectors is configured to periodically collect power management related data from the corresponding subsystem, and to format the collected power management related data for conveyance along any one of a plurality of channels between the local data collector and the system collector. The system collector is coupled with the plurality of local data collectors via the plurality of channels. The system collector selects from the channels between the system collector and each of the local data collectors based, at least in part, on channel states, and retrieves the power management related data collected by each of the local data collectors along a selected channel for the local data collector.Type: GrantFiled: November 27, 2012Date of Patent: February 2, 2016Assignee: International Business Machines CorporationInventors: Irving Baysah, John S. Dodson, Karthick Rajamani, Eric E. Retter, Gregory S. Still, Malcolm S. Allen-Ware, Scot H. Rider, Todd J. Rosedahl, Gary Van Huben
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Patent number: 9158698Abstract: According to an embodiment, a computer-implemented method for control block management is provided. The computer-implemented method includes placing one or more control blocks in a queue for execution by a computer hardware device. The computer-implemented method also includes allocating a purge flag in each of the control blocks. The purge flag instructs the computer hardware device to skip execution of the corresponding control block.Type: GrantFiled: March 15, 2013Date of Patent: October 13, 2015Assignee: International Business Machines CorporationInventors: Michael J. Cadigan, Jr., Scot H. Rider, Donald W. Schmidt
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Patent number: 9146817Abstract: Embodiments relate to collecting extended error data from units within a programmable device. A pointer is accessed that points to a region of memory that contains a list of entries that references the extended error data. The list of entries is walked by adjusting a read pointer to obtain the extended error data. The referenced extended error data is moved to an event log.Type: GrantFiled: March 13, 2013Date of Patent: September 29, 2015Assignee: International Business Machines CorporationInventors: Michael C. Cadigan, Jr., Howard M. Haynie, Scot H. Rider, Mushfiq U. Saleheen
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Patent number: 9142272Abstract: Embodiments relate to a dual asynchronous and synchronous memory system. One aspect is a system that includes a memory controller and a memory buffer chip coupled to the memory controller via a synchronous channel. The memory buffer chip includes a memory buffer unit configured to synchronously communicate with the memory controller in a nest domain, and a memory buffer adaptor configured to communicate with at least one memory interface port in a memory domain. The at least one memory interface port is operable to access at least one memory device. A boundary layer is connected to the nest domain and the memory domain, where the boundary layer is configurable to operate in a synchronous transfer mode between the nest and memory domains and to operate in an asynchronous transfer mode between the nest and memory domains.Type: GrantFiled: March 15, 2013Date of Patent: September 22, 2015Assignee: International Business Machines CorporationInventors: Gary A. Van Huben, Patrick J. Meaney, John S. Dodson, Scot H. Rider, James C. Gregerson, Eric E. Retter, Irving G. Baysah, Glenn D. Gilda, Lawrence D. Curley, Vesselina K. Papazova
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Publication number: 20150058848Abstract: Embodiments relate to a method for encapsulating a hardware application for virtualization. The method surrounds the hardware application with a service layer controller and ring interfaces. The ring interfaces dictates a virtual function that the hardware application is running. The method controls the hardware application so that the hardware application is reset in between each of a plurality of running jobs. The method tags, by the ring interfaces, each of a plurality of requests with an identifier signifying a virtual function that the respective request belongs to. The method ensures that there are not any outstanding requests following a quiesce of the hardware application.Type: ApplicationFiled: September 30, 2014Publication date: February 26, 2015Inventors: Michael J. Cadigan, JR., Howard M. Haynie, Scot H. Rider, Mushfiq U. Saleheen, Donald W. Schmidt
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Publication number: 20150019831Abstract: A computer-system implemented method for dual asynchronous and synchronous memory operation in a memory subsystem includes establishing a synchronous channel between a memory controller and a memory buffer chip. A mode selector determines a reference clock source for a memory domain phase-locked loop of the memory buffer chip based on an operating mode of the memory buffer chip. An output of a nest domain phase-locked loop is provided as the reference clock source to the memory domain phase-locked loop in the memory buffer chip based on the operating mode being synchronous. The nest domain phase-locked loop is operable synchronous to a memory controller phase-locked loop of the memory controller. A separate reference clock is provided independent of the nest domain phase-locked loop as the reference clock to the memory domain phase-locked loop based on the operating mode being asynchronous.Type: ApplicationFiled: September 30, 2014Publication date: January 15, 2015Inventors: Gary A. Van Huben, Patrick J. Meaney, John S. Dodson, Scot H. Rider, James C. Gregerson, Eric E. Retter, Irving G. Baysah, Glenn D. Gilda, Lawrence D. Curley, Vesselina K. Papazova
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Publication number: 20150020192Abstract: Embodiments relate an address translation/specification (ATS) field. An aspect includes receiving a work queue entry from a work queue in a main memory by a hardware accelerator, the work queue entry corresponding to an operation of the hardware accelerator that is requested by user-space software, the work queue entry comprising a first ATS field that describes a structure of the work queue entry. Another aspect includes, based on determining that the first ATS field is consistent with the operation corresponding to the work queue entry and the structure of the work queue entry, executing the operation corresponding to the work queue entry by the hardware accelerator. Another aspect includes, based on determining that the first ATS field is not consistent with the operation corresponding to the work queue entry and the structure of the work queue entry, rejecting the work queue entry by the hardware accelerator.Type: ApplicationFiled: September 30, 2014Publication date: January 15, 2015Inventors: Frank Haverkamp, Christian Jacobi, Scot H. Rider, Vikramjit Sethi, Randal C. Swanberg, Joerg-Stephan Vogt
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Publication number: 20140380319Abstract: Embodiments relate an address translation/specification (ATS) field. An aspect includes receiving a work queue entry from a work queue in a main memory by a hardware accelerator, the work queue entry corresponding to an operation of the hardware accelerator that is requested by user-space software, the work queue entry comprising a first ATS field that describes a structure of the work queue entry. Another aspect includes, based on determining that the first ATS field is consistent with the operation corresponding to the work queue entry and the structure of the work queue entry, executing the operation corresponding to the work queue entry by the hardware accelerator. Another aspect includes, based on determining that the first ATS field is not consistent with the operation corresponding to the work queue entry and the structure of the work queue entry, rejecting the work queue entry by the hardware accelerator.Type: ApplicationFiled: June 20, 2013Publication date: December 25, 2014Inventors: Frank Haverkamp, Christian Jacobi, Scot H. Rider, Vikramjit Sethi, Randal C. Swanberg, Joerg-Stephan Vogt
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Publication number: 20140281253Abstract: According to an embodiment, a computer-implemented method for control block management is provided. The computer-implemented method includes placing one or more control blocks in a queue for execution by a computer hardware device. The computer-implemented method also includes allocating a purge flag in each of the control blocks. The purge flag instructs the computer hardware device to skip execution of the corresponding control block.Type: ApplicationFiled: March 15, 2013Publication date: September 18, 2014Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Michael J. Cadigan, JR., Scot H. Rider, Donald W. Schmidt
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Publication number: 20140282506Abstract: Embodiments relate to a computer system comprising a service layer controller. The computer system comprises a ring interface unit configured to provide access to a host system that enables access to a plurality of virtual machines (VMs). The computer system comprises a hardware application configured to be encapsulated by the service layer controller such that the hardware application communicates to the host system via interfaces controlled by the ring interface unit and service layer controller.Type: ApplicationFiled: March 14, 2013Publication date: September 18, 2014Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Michael J. Cadigan, Jr., Howard M. Haynie, Scot H. Rider, Mushfiq U. Saleheen, Donald W. Schmidt
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Publication number: 20140281326Abstract: Embodiments relate to a dual asynchronous and synchronous memory system. One aspect is a system that includes a memory controller and a memory buffer chip coupled to the memory controller via a synchronous channel. The memory buffer chip includes a memory buffer unit configured to synchronously communicate with the memory controller in a nest domain, and a memory buffer adaptor configured to communicate with at least one memory interface port in a memory domain. The at least one memory interface port is operable to access at least one memory device. A boundary layer is connected to the nest domain and the memory domain, where the boundary layer is configurable to operate in a synchronous transfer mode between the nest and memory domains and to operate in an asynchronous transfer mode between the nest and memory domains.Type: ApplicationFiled: March 15, 2013Publication date: September 18, 2014Applicant: International Business Machines CorporationInventors: Gary A. Van Huben, Patrick J. Meaney, John S. Dodson, Scot H. Rider, James C. Gregerson, Eric E. Retter, Irving G. Baysah, Glenn D. Gilda, Lawrence D. Curley, Vesselina K. Papazova