Patents by Inventor Scot Kellar

Scot Kellar has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10068866
    Abstract: An integrated circuit (IC) packaging arrangement for surface mounting of the IC includes a package body that encapsulates one or more IC dies. The package body according to some embodiments has rectangular aspect ratio with a length dimension and a width dimension of different size. The IC packaging according to some embodiments includes leadless surface-mount electrical contacts. According to some embodiments, the leadless surface-mount contacts are situated in clusters at opposite ends of the length dimension of the IC body.
    Type: Grant
    Filed: September 29, 2016
    Date of Patent: September 4, 2018
    Assignee: Intel Corporation
    Inventors: Scot A Kellar, Darren S Crews
  • Publication number: 20180090462
    Abstract: An integrated circuit (IC) packaging arrangement for surface mounting of the IC includes a package body that encapsulates one or more IC dies. The package body according to some embodiments has rectangular aspect ratio with a length dimension and a width dimension of different size. The IC packaging according to some embodiments includes leadless surface-mount electrical contacts. According to some embodiments, the leadless surface-mount contacts are situated in clusters at opposite ends of the length dimension of the IC body.
    Type: Application
    Filed: September 29, 2016
    Publication date: March 29, 2018
    Inventors: Scot A. Kellar, Darren S. Crews
  • Patent number: 7271434
    Abstract: The present invention discloses a method including providing a substrate; forming a lower conductor over the substrate; forming a conducting nanostructure over the lower conductor; forming a thin dielectric over the conducting nanostructure; and forming an upper conductor over the thin dielectric. The present invention further discloses a device including a substrate; a lower conductor located over the substrate; a conducting nanostructure located over the lower conductor; a thin dielectric located over the conducting nanostructure; and an upper conductor located over the thin dielectric.
    Type: Grant
    Filed: December 17, 2003
    Date of Patent: September 18, 2007
    Assignee: Intel Corporation
    Inventors: Scot A. Kellar, Sarah E. Kim
  • Patent number: 7265406
    Abstract: The present invention discloses a method including providing a substrate; forming a lower conductor over the substrate; forming a conducting nanostructure over the lower conductor; forming a thin dielectric over the conducting nanostructure; and forming an upper conductor over the thin dielectric. The present invention further discloses a device including a substrate; a lower conductor located over the substrate; a conducting nanostructure located over the lower conductor; a thin dielectric located over the conducting nanostructure; and an upper conductor located over the thin dielectric.
    Type: Grant
    Filed: May 9, 2005
    Date of Patent: September 4, 2007
    Assignee: Intel Corporation
    Inventors: Scot A. Kellar, Sarah E. Kim
  • Patent number: 7244983
    Abstract: Apparatus for an on-chip decoupling capacitor. The capacitor includes a bottom electrode that consist of nanostructures deposited over a planarized metal, a dielectric material deposited over the nanostructures, and a top electrode deposited over the dielectric material. The shape of the bottom electrode is tunable by modulating the diameter and/or the length of the nanostructures to produce an increase in capacitance without increasing the footprint of the on-chip decoupling capacitor.
    Type: Grant
    Filed: April 23, 2003
    Date of Patent: July 17, 2007
    Assignee: Intel Corporation
    Inventors: Sarah E. Kim, Scot A. Kellar
  • Publication number: 20070111386
    Abstract: A method of vertically stacking wafers is provided to form three-dimensional (3D) wafer stack. Such method comprising: selectively depositing a plurality of metallic lines on opposing surfaces of adjacent wafers; bonding the adjacent wafers, via the metallic lines, to establish electrical connections between active devices on vertically stacked wafers; and forming one or more vias to establish electrical connections between the active devices on the vertically stacked wafers and an external interconnect. Metal bonding areas on opposing surfaces of the adjacent wafers can be increased by using one or more dummy vias, tapered vias, or incorporating an existing copper (Cu) dual damascene process.
    Type: Application
    Filed: November 21, 2006
    Publication date: May 17, 2007
    Inventors: Sarah Kim, R. List, Scot Kellar
  • Patent number: 7157787
    Abstract: A method of vertically stacking wafers is provided to form three-dimensional (3D) wafer stack. Such method comprising: selectively depositing a plurality of metallic lines on opposing surfaces of adjacent wafers; bonding the adjacent wafers, via the metallic lines, to establish electrical connections between active devices on vertically stacked wafers; and forming one or more vias to establish electrical connections between the active devices on the vertically stacked wafers and an external interconnect. Metal bonding areas on opposing surfaces of the adjacent wafers can be increased by using one or more dummy vias, tapered vias, or incorporating an existing copper (Cu) dual damascene process.
    Type: Grant
    Filed: May 26, 2004
    Date of Patent: January 2, 2007
    Assignee: Intel Corporation
    Inventors: Sarah E. Kim, R. Scott List, Scot A. Kellar
  • Patent number: 7091084
    Abstract: The present invention discloses a method including providing a substrate; forming a lower conductor over the substrate; forming a conducting nanostructure over the lower conductor; forming a thin dielectric over the conducting nanostructure; and forming an upper conductor over the thin dielectric. The present invention further discloses a device including a substrate; a lower conductor located over the substrate; a conducting nanostructure located over the lower conductor; a thin dielectric located over the conducting nanostructure; and an upper conductor located over the thin dielectric.
    Type: Grant
    Filed: January 26, 2005
    Date of Patent: August 15, 2006
    Assignee: Intel Corporation
    Inventors: Scot A. Kellar, Sarah E. Kim
  • Patent number: 7056807
    Abstract: A three-dimensional (3-D) integrated chip system is provided with a first wafer including one or more integrated circuit (IC) devices, metallic lines deposited via an interlevel dielectric (ILD) on a surface, and at least one barrier line deposited on an outer edge of the surface; and a second wafer including one or more integrated circuit (IC) devices, metallic lines deposited via an interlevel dielectric (ILD) on a surface, and at least one barrier line deposited on an outer edge of the surface, wherein the metallic lines and the barrier line deposited on the surface of the second wafer are bonded with the metallic lines and the barrier line deposited on the surface of the first wafer to establish electrical connections between active IC devices on adjacent wafers and to form a barrier structure on the outer edge of the adjacent wafers.
    Type: Grant
    Filed: July 7, 2003
    Date of Patent: June 6, 2006
    Assignee: Intel Corporation
    Inventors: Scot A. Kellar, Sarah E. Kim, R. Scott List
  • Patent number: 7037804
    Abstract: A three-dimensional (3-D) integrated chip system is provided with a first wafer including one or more integrated circuit (IC) devices; a second wafer including one or more integrated circuit (IC) devices; and a metal bonding layer deposited on opposing surfaces of the first and second wafers at designated locations to establish electrical connections between active IC devices on the first and second wafers and to provide metal bonding between the adjacent first and second wafers, when the first wafer is pressed against the second wafer using a flexible bladder press to account for height differences of the metal bonding layer across the opposing surfaces of the first and second wafers.
    Type: Grant
    Filed: October 27, 2003
    Date of Patent: May 2, 2006
    Assignee: Intel Corporation
    Inventors: Scot A. Kellar, Sarah E. Kim, R. Scott List
  • Patent number: 6975016
    Abstract: A three-dimensional (3-D) integrated chip system is provided with a first wafer including one or more integrated circuit (IC) devices; a second wafer including one or more integrated circuit (IC) devices; and a metal bonding layer deposited on opposing surfaces of the first and second wafers at designated locations to establish electrical connections between active IC devices on the first and second wafers and to provide metal bonding between the adjacent first and second wafers, when the first wafer is pressed against the second wafer using a flexible bladder press to account for height differences of the metal bonding layer across the opposing surfaces of the first and second wafers.
    Type: Grant
    Filed: February 6, 2002
    Date of Patent: December 13, 2005
    Assignee: Intel Corporation
    Inventors: Scot A. Kellar, Sarah E. Kim, R. Scott List
  • Publication number: 20050194628
    Abstract: The present invention discloses a method including providing a substrate; forming a lower conductor over the substrate; forming a conducting nanostructure over the lower conductor; forming a thin dielectric over the conducting nanostructure; and forming an upper conductor over the thin dielectric. The present invention further discloses a device including a substrate; a lower conductor located over the substrate; a conducting nanostructure located over the lower conductor; a thin dielectric located over the conducting nanostructure; and an upper conductor located over the thin dielectric.
    Type: Application
    Filed: May 9, 2005
    Publication date: September 8, 2005
    Inventors: Scot Kellar, Sarah Kim
  • Publication number: 20050151261
    Abstract: The present invention discloses a method including providing a substrate; forming a lower conductor over the substrate; forming a conducting nanostructure over the lower conductor; forming a thin dielectric over the conducting nanostructure; and forming an upper conductor over the thin dielectric. The present invention further discloses a device including a substrate; a lower conductor located over the substrate; a conducting nanostructure located over the lower conductor; a thin dielectric located over the conducting nanostructure; and an upper conductor located over the thin dielectric.
    Type: Application
    Filed: January 26, 2005
    Publication date: July 14, 2005
    Inventors: Scot Kellar, Sarah Kim
  • Patent number: 6911373
    Abstract: The present invention discloses a method including providing a substrate; forming a lower conductor over the substrate; forming a conducting nanostructure over the lower conductor; forming a thin dielectric over the conducting nanostructure; and forming an upper conductor over the thin dielectric. The present invention further discloses a device including a substrate; a lower conductor located over the substrate; a conducting nanostructure located over the lower conductor; a thin dielectric located over the conducting nanostructure; and an upper conductor located over the thin dielectric.
    Type: Grant
    Filed: September 20, 2002
    Date of Patent: June 28, 2005
    Assignee: Intel Corporation
    Inventors: Scot A. Kellar, Sarah E. Kim
  • Publication number: 20050101099
    Abstract: Apparatus for an on-chip decoupling capacitor. The capacitor includes a bottom electrode that consist of nanostructures deposited over a planarized metal, a dielectric material deposited over the nanostructures, and a top electrode deposited over the dielectric material. The shape of the bottom electrode is tunable by modulating the diameter and/or the length of the nanostructures to produce an increase in capacitance without increasing the footprint of the on-chip decoupling capacitor.
    Type: Application
    Filed: April 23, 2003
    Publication date: May 12, 2005
    Inventors: Sarah Kim, Scot Kellar
  • Patent number: 6887769
    Abstract: A three-dimensional (3-D) integrated chip system is provided with a first wafer including one or more integrated circuit (IC) devices; a second wafer including one or more integrated circuit (IC) devices; and metallic lines deposited on opposing surfaces of the first and second wafers at designated locations with an interlevel dielectric (ILD) recess surrounding the metallic lines to facilitate direct metal bonding between the first and second wafers and establish electrical connections between active IC devices on the first and second wafers.
    Type: Grant
    Filed: February 6, 2002
    Date of Patent: May 3, 2005
    Assignee: Intel Corporation
    Inventors: Scot A. Kellar, Sarah E. Kim, R. Scott List
  • Publication number: 20040219763
    Abstract: A method of vertically stacking wafers is provided to form three-dimensional (3D) wafer stack. Such method comprising: selectively depositing a plurality of metallic lines on opposing surfaces of adjacent wafers; bonding the adjacent wafers, via the metallic lines, to establish electrical connections between active devices on vertically stacked wafers; and forming one or more vias to establish electrical connections between the active devices on the vertically stacked wafers and an external interconnect. Metal bonding areas on opposing surfaces of the adjacent wafers can be increased by using one or more dummy vias, tapered vias, or incorporating an existing copper (Cu) dual damascene process.
    Type: Application
    Filed: May 26, 2004
    Publication date: November 4, 2004
    Inventors: Sarah E. Kim, R. Scott List, Scot A. Kellar
  • Publication number: 20040142540
    Abstract: A three-dimensional (3-D) integrated chip system is provided with a first wafer including one or more integrated circuit (IC) devices; a second wafer including one or more integrated circuit (IC) devices; and a metal bonding layer deposited on opposing surfaces of the first and second wafers at designated locations to establish electrical connections between active IC devices on the first and second wafers and to provide metal bonding between the adjacent first and second wafers, when the first wafer is pressed against the second wafer using a flexible bladder press to account for height differences of the metal bonding layer across the opposing surfaces of the first and second wafers.
    Type: Application
    Filed: October 27, 2003
    Publication date: July 22, 2004
    Inventors: Scot A. Kellar, Sarah E. Kim, R. Scott List
  • Patent number: 6762076
    Abstract: A method of vertically stacking wafers is provided to form three-dimensional (3D) wafer stack. Such method comprising: selectively depositing a plurality of metallic lines on opposing surfaces of adjacent wafers; bonding the adjacent wafers, via the metallic lines, to establish electrical connections between active devices on vertically stacked wafers; and forming one or more vias to establish electrical connections between the active devices on the vertically stacked wafers and an external interconnect. Metal bonding areas on opposing surfaces of the adjacent wafers can be increased by using one or more dummy vias, tapered vias, or incorporating an existing copper (Cu) dual damascene process.
    Type: Grant
    Filed: February 20, 2002
    Date of Patent: July 13, 2004
    Assignee: Intel Corporation
    Inventors: Sarah E. Kim, R. Scott List, Scot A. Kellar
  • Publication number: 20040131774
    Abstract: The present invention discloses a method including providing a substrate; forming a lower conductor over the substrate; forming a conducting nanostructure over the lower conductor; forming a thin dielectric over the conducting nanostructure; and forming an upper conductor over the thin dielectric.
    Type: Application
    Filed: December 17, 2003
    Publication date: July 8, 2004
    Inventors: Scot A. Kellar, Sarah E. Kim