Patents by Inventor Scot Kellar

Scot Kellar has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12242315
    Abstract: A thermal management scheme, for a multichip module, that is aware of various dies in a stack (horizontal and/or vertical) and heat generated from them, local hot spots in a victim die, and hot spots in aggressor die(s). Each victim die receives telemetry information from thermal sensors located in aggressor dies as well as local thermal sensors in the victim die. The telemetry information is used to enable a virtual sensing scheme where temperature for a target die (e.g., a victim die) and/or its intellectual property (IP) domain is estimated or calculated. The estimated or calculated temperature is then used for performance management of the victim and/or aggressor dies in the stack.
    Type: Grant
    Filed: March 16, 2021
    Date of Patent: March 4, 2025
    Assignee: Intel Corporation
    Inventors: Somvir Singh Dahiya, Stephen Gunther, Julien Sebot, Randy Osborne, Scot Kellar, Joshua Een
  • Publication number: 20240329722
    Abstract: An apparatus and method to control temperature ramp rates including temperature spike detection and control. For example, one embodiment of a processor comprises: a plurality of cores to execute instructions; a power management unit to control power consumption of each core of the plurality of cores, the power management unit comprising: a frequency ramp governor or power step governor to determine a frequency ramp rate limit or power step limit for a core of the plurality of cores based, at least in part, on a present frequency or present power metrics of the core; a frequency limiter or voltage limiter to determine a maximum frequency or maximum voltage of the core based, at least in part, on a measured temperature; and limit resolution circuitry to determine a first frequency or a first power level of the core in accordance with the frequency ramp rate limit or the power step limit and the maximum frequency or maximum voltage.
    Type: Application
    Filed: March 30, 2023
    Publication date: October 3, 2024
    Inventors: Somvir DAHIYA, Scot KELLAR, Stephen H. GUNTHER, Mark GALLINA, Efraim ROTEM, Prasanna JOTHI
  • Publication number: 20240063091
    Abstract: Microelectronic devices, assemblies, and systems include a multichip composite device having one or more chiplets bonded to a base die and an inorganic dielectric material adjacent the chiplets and over the base die. The multichip composite device is coupled to a structural member that is made of or includes a heat conducting material, or has integrated fluidic cooling channels to conduct heat from the chiplets and the base die.
    Type: Application
    Filed: August 19, 2022
    Publication date: February 22, 2024
    Applicant: Intel Corporation
    Inventors: Adel Elsherbini, Feras Eid, Scot Kellar, Yoshihiro Tomita, Rajiv Mongia, Kimin Jun, Shawna Liff, Wenhao Li, Johanna Swan, Bhaskar Jyoti Krishnatreya, Debendra Mallik, Krishna Vasanth Valavala, Lei Jiang, Xavier Brun, Mohammad Enamul Kabir, Haris Khan Niazi, Jiraporn Seangatith, Thomas Sounart
  • Publication number: 20220300049
    Abstract: A thermal management scheme, for a multichip module, that is aware of various dies in a stack (horizontal and/or vertical) and heat generated from them, local hot spots in a victim die, and hot spots in aggressor die(s). Each victim die receives telemetry information from thermal sensors located in aggressor dies as well as local thermal sensors in the victim die. The telemetry information is used to enable a virtual sensing scheme where temperature for a target die (e.g., a victim die) and/or its intellectual property (IP) domain is estimated or calculated. The estimated or calculated temperature is then used for performance management of the victim and/or aggressor dies in the stack.
    Type: Application
    Filed: March 16, 2021
    Publication date: September 22, 2022
    Applicant: Intel Corporation
    Inventors: Somvir Singh Dahiya, Stephen Gunther, Julien Sebot, Randy Osborne, Scot Kellar, Joshua Een
  • Publication number: 20070111386
    Abstract: A method of vertically stacking wafers is provided to form three-dimensional (3D) wafer stack. Such method comprising: selectively depositing a plurality of metallic lines on opposing surfaces of adjacent wafers; bonding the adjacent wafers, via the metallic lines, to establish electrical connections between active devices on vertically stacked wafers; and forming one or more vias to establish electrical connections between the active devices on the vertically stacked wafers and an external interconnect. Metal bonding areas on opposing surfaces of the adjacent wafers can be increased by using one or more dummy vias, tapered vias, or incorporating an existing copper (Cu) dual damascene process.
    Type: Application
    Filed: November 21, 2006
    Publication date: May 17, 2007
    Inventors: Sarah Kim, R. List, Scot Kellar
  • Publication number: 20050194628
    Abstract: The present invention discloses a method including providing a substrate; forming a lower conductor over the substrate; forming a conducting nanostructure over the lower conductor; forming a thin dielectric over the conducting nanostructure; and forming an upper conductor over the thin dielectric. The present invention further discloses a device including a substrate; a lower conductor located over the substrate; a conducting nanostructure located over the lower conductor; a thin dielectric located over the conducting nanostructure; and an upper conductor located over the thin dielectric.
    Type: Application
    Filed: May 9, 2005
    Publication date: September 8, 2005
    Inventors: Scot Kellar, Sarah Kim
  • Publication number: 20050151261
    Abstract: The present invention discloses a method including providing a substrate; forming a lower conductor over the substrate; forming a conducting nanostructure over the lower conductor; forming a thin dielectric over the conducting nanostructure; and forming an upper conductor over the thin dielectric. The present invention further discloses a device including a substrate; a lower conductor located over the substrate; a conducting nanostructure located over the lower conductor; a thin dielectric located over the conducting nanostructure; and an upper conductor located over the thin dielectric.
    Type: Application
    Filed: January 26, 2005
    Publication date: July 14, 2005
    Inventors: Scot Kellar, Sarah Kim
  • Publication number: 20050101099
    Abstract: Apparatus for an on-chip decoupling capacitor. The capacitor includes a bottom electrode that consist of nanostructures deposited over a planarized metal, a dielectric material deposited over the nanostructures, and a top electrode deposited over the dielectric material. The shape of the bottom electrode is tunable by modulating the diameter and/or the length of the nanostructures to produce an increase in capacitance without increasing the footprint of the on-chip decoupling capacitor.
    Type: Application
    Filed: April 23, 2003
    Publication date: May 12, 2005
    Inventors: Sarah Kim, Scot Kellar