Abstract: A device and methods are disclosed for communicating an unrounded result from one arithmetic calculation for use in a second, subsequent calculation. For example, an unrounded result of a first calculation can be forwarded to provide a multiplier, a multiplicand or an addend operand for the subsequent operation. The operand can be forwarded to the input of the same fused multiply addition module (FMAM) that supplied the result, or to another FMAM, and do so without regard to the precision of the forwarded operand, the precision of the subsequent operation, or the native precision of the FMAM.

Abstract: An arithmetic processing unit is disclosed that can perform multiply operations, addition operations, or a combination thereof. The arithmetic processing unit can operate in two modes. The first mode supports one single, double, or extended-precision computation, and the second mode supports two simultaneous single-precision computations using the same exponent and mantissa datapaths.

Abstract: In a hardware floating point adder, each operand exponent is logically divided into fields. The corresponding fields of each exponent are input to a separate shift logic circuit which determines a relative amount to shift the operand mantissa without reference to any carry bit from a lower order field. Both mantissas are potentially shifted, each by one or more shift logic circuit outputs, making it possible to perform some of the shifts simultaneously. Using 11 bit exponents in accordance with ANSI/IEEE Standard 754-1985, double format for 64-bit numbers, operand registers are logically divided into: field #3, consisting the lowest two order bits; field #2 consisting of the next lowest two order bits after the first two; and field #1 consisting of the highest 7 order bits. The shift logic circuit for field #3 shifts and Operand A mantissa, right or left, 0, 1, 2 or 3 bits. The shift logic circuit for field #2 simultaneously shifts an Operand B mantissa, right or left, 0, 4, 8 or 12 bits.

Abstract: An apparatus and method for determining the difference between two exponents of two floating point numbers is disclosed. The exponent of each number is split into two portions. A high portion contains the most significant bits and a low portion contains the least significant bits. The number of bits in the low portion is related to the number of bits in the fraction portion of each floating point number. To determine differences that require a shift in one of the exponenets, one of the differences between the low portions of the exponents is selected based upon which of several conditions are found with respect to the difference between the high portion. Advantageously, a set of adders which are as wide as the number of bits in the low portion of each exponent are used.

Abstract: A tightly-coupled main processor and coprocessor overlap the execution of sequential instructions when apparent sequential operation and precise exception interrupts can be assured. Logic detects all conditions under which these criteria might potentially be violated in the coprocessor before it has finished performing an instruction, and holds off the main processor from executing a subsequent instruction.

Abstract: Apparatus for enhancing certain floating point arithmetic operations, by examining the initial operands and the exponent and fractional results and predicting when the steps of postnormalization and rounding can be skipped. The fraction result format enables a prediction of normalization and rounding under each of the addition, subtraction and multiplication possibilities, and under each of the various choices of rounding mode which are used in floating point arithmetic.

Abstract: A method and apparatus for processing postnormalization and rounding in parallel in floating point arithmetic circuits. The fractional result of a floating point arithmetic operation is simultaneously passed to a normalized circuit and a round circuit, and the first two bit positions of the fractional result are examined. If the 2-bit format is 1.X the round circuit is activated; if the 2-bit format is 0.1X the fractional result is shifted left one position and the round circuit is activated; if the 2-bit format is in neither of the above formats the normalize circuit is activated. In no event is it necessary to activate sequentially the normalize circuit and the round circuit.

Abstract: An apparatus for determining the correct value to be assigned to the "sticky-bit" (S) position as a consequence of an arithmetic floating point multiply, divide or square root operation. The apparatus measures the number of trailing zeroes in the operand registers, performs a sum or difference calculation of these values, and compares the result with a third value to determine the sticky-bit value.