Patents by Inventor Scott A. Weber
Scott A. Weber has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11651111Abstract: An apparatus to facilitate enabling secure state-clean during configuration of partial reconfiguration bitstreams on accelerator devices is disclosed. The apparatus includes a security engine to receive an incoming partial reconfiguration (PR) bitstream corresponding to a new PR persona to configure a region of the apparatus; perform, as part of a PR configuration sequence for the new PR persona, a first clear operation to clear previously-set persona configuration bits in the region; perform, as part of the PR configuration sequence subsequent to the first clear operation, a set operation to set new persona configuration bits in the region; and perform, as part of the PR configuration sequence, a second clear operation to clear memory blocks of the region that became unfrozen subsequent to the set operation, the second clear operation performed using a persona-dependent mask corresponding to the new PR persona.Type: GrantFiled: December 21, 2020Date of Patent: May 16, 2023Assignee: INTEL CORPORATIONInventors: Alpa Trivedi, Scott Weber, Steffen Schulz, Patrick Koeberl
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Publication number: 20230131938Abstract: An integrated circuit includes a buffer circuit, a memory circuit, and a controller circuit that determines if the memory circuit stores information that is valid and determines whether to transmit the information stored in the memory circuit to the buffer circuit based on credits that indicate an amount of storage space available in the buffer circuit. The controller circuit transmits the information to the buffer circuit if the credits indicate that sufficient storage space is available in the buffer circuit to store the information.Type: ApplicationFiled: December 21, 2022Publication date: April 27, 2023Applicant: Intel CorporationInventors: Scott Weber, Chang Kian Tan, Rajiv Kumar, Saravanan Sethuraman
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Publication number: 20230107106Abstract: Embodiments disclosed herein include electronic packages. In an embodiment, the electronic package comprises, a package substrate, an interposer on the package substrate, a first die cube and a second die cube on the interposer, wherein the interposer includes conductive traces for electrically coupling the first die cube to the second die cube, a die on the package substrate, and an embedded multi-die interconnect bridge (EMIB) in the package substrate, wherein the EMIB electrically couples the interposer to the die.Type: ApplicationFiled: December 12, 2022Publication date: April 6, 2023Inventors: MD Altaf HOSSAIN, Ankireddy NALAMALPU, Dheeraj SUBBAREDDY, Robert SANKMAN, Ravindranath V. MAHAJAN, Debendra MALLIK, Ram S. VISWANATH, Sandeep B. SANE, Sriram SRINIVASAN, Rajat AGARWAL, Aravind DASU, Scott WEBER, Ravi GUTALA
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Publication number: 20230089869Abstract: An apparatus to facilitate scalable runtime validation for on-device design rule checks is disclosed. The apparatus includes a memory to store a contention set, multiplexers, and a validator. In one implementation, the validator is to: receive design rule information for the multiplexers, the design rule information referencing the contention set, wherein the contention set identifies a determined harmful bitstream configuration for each multiplexer instance of the multiplexers, and wherein the contention set comprises a mapping of contents of a user bitstream to configuration bits of the multiplexers; receive, at the validator of the apparatus, the user bitstream for programming the multiplexers of the apparatus; analyze, at the validator using the design rule information, the user bitstream against the contention set at a programming time of the apparatus; and provide an error indication responsive to identifying a match between the user bitstream and the contention set.Type: ApplicationFiled: November 29, 2022Publication date: March 23, 2023Applicant: Intel CorporationInventors: Furkan Turan, Patrick Koeberl, Alpa Trivedi, Steffen Schulz, Scott Weber
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Patent number: 11557541Abstract: Embodiments disclosed herein include electronic packages. In an embodiment, the electronic package comprises, a package substrate, an interposer on the package substrate, a first die cube and a second die cube on the interposer, wherein the interposer includes conductive traces for electrically coupling the first die cube to the second die cube, a die on the package substrate, and an embedded multi-die interconnect bridge (EMIB) in the package substrate, wherein the EMIB electrically couples the interposer to the die.Type: GrantFiled: December 28, 2018Date of Patent: January 17, 2023Assignee: Intel CorporationInventors: Md Altaf Hossain, Ankireddy Nalamalpu, Dheeraj Subbareddy, Robert Sankman, Ravindranath V. Mahajan, Debendra Mallik, Ram S. Viswanath, Sandeep B. Sane, Sriram Srinivasan, Rajat Agarwal, Aravind Dasu, Scott Weber, Ravi Gutala
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Patent number: 11556677Abstract: An apparatus to facilitate scalable runtime validation for on-device design rule checks is disclosed. The apparatus includes a memory to store a contention set, one or more multiplexors, and a validator communicably coupled to the memory. In one implementation, the validator is to: receive design rule information for the one or more multiplexers, the design rule information referencing the contention set; analyze, using the design rule information, a user bitstream against the contention set at a programming time of the apparatus, the user bitstream for programming the one or more multiplexors; and provide an error indication responsive to identifying a match between the user bitstream and the contention set.Type: GrantFiled: December 23, 2020Date of Patent: January 17, 2023Assignee: INTEL CORPORATIONInventors: Furkan Turan, Patrick Koeberl, Alpa Trivedi, Steffen Schulz, Scott Weber
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Publication number: 20220405005Abstract: A three dimensional circuit system includes a first integrated circuit die having a core logic region that has first memory circuits and logic circuits. The three dimensional circuit system includes a second integrated circuit die that has second memory circuits. The first and second integrated circuit dies are coupled together in a vertically stacked configuration. The three dimensional circuit system includes third memory circuits coupled to the first integrated circuit die. The third memory circuits reside in a plane of the first integrated circuit die. The logic circuits are coupled to access the first, second, and third memory circuits and data can move between the first, second, and third memories. The third memory circuits have a larger memory capacity and a smaller memory access bandwidth than the second memory circuits. The second memory circuits have a larger memory capacity and a smaller memory access bandwidth than the first memory circuits.Type: ApplicationFiled: June 16, 2021Publication date: December 22, 2022Applicant: Intel CorporationInventors: Scott Weber, Jawad Khan, Ilya Ganusov, Martin Langhammer, Matthew Adiletta, Terence Magee, Albert Fazio, Richard Coulson, Ravi Gutala, Aravind Dasu, Mahesh Iyer
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Publication number: 20220372170Abstract: Modified macrophage immune cells are provided for treatment of cancer and other diseases. In particular said macrophages express chimeric antigen receptors (CAR). The single chain variable fragment (scFv) may be directed against thymidine kinase 1 (TK1) or hypoxanthine guanine phosphoribosyltransferase (HPRT). The signaling domain may be derived from a Toll-like receptor (TLR).Type: ApplicationFiled: June 6, 2022Publication date: November 24, 2022Inventors: Kim Leslie O'Neill, Scott Weber
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Patent number: 11487445Abstract: A system may include a host processor, a coprocessor for accelerating tasks received from the host processor, and one or more memory dies mounted to the coprocessor. The coprocessor and the memory die may be part of an integrated circuit package. The memory die may convey configuration bit streams to one or more logic sectors in programmable circuitry of the coprocessor over through-silicon vias. Each logic sector may include one or more data registers that are loaded with configuration data from the memory die. Multiple data registers may be loaded with configuration data simultaneously. The configuration data may be loaded onto an array of configuration memory cells using the data registers. Multiple data registers may be pipelined to allow simultaneous loading of configuration data into multiple sub-arrays of the array of configuration memory cells.Type: GrantFiled: November 22, 2016Date of Patent: November 1, 2022Assignee: Intel CorporationInventors: Aravind Dasu, Scott Weber, Jun Pin Tan, Arifur Rahman
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Patent number: 11489527Abstract: A three dimensional circuit system includes first and second integrated circuit (IC) dies. The first IC die includes programmable logic circuits arranged in sectors and first programmable interconnection circuits having first router circuits. The second IC die includes non-programmable circuits arranged in regions and second programmable interconnection circuits having second router circuits. Each of the regions in the second IC die is vertically aligned with at least one of the sectors in the first IC die. Each of the second router circuits is coupled to one of the first router circuits through a vertical die-to-die connection. The first and second programmable interconnection circuits are programmable to route signals between the programmable logic circuits and the non-programmable circuits through the first and second router circuits. The circuit system may include additional IC dies. The first and second IC dies and any additional IC dies are coupled in a vertically stacked configuration.Type: GrantFiled: June 22, 2021Date of Patent: November 1, 2022Assignee: Intel CorporationInventors: Scott Weber, Aravind Dasu, Ravi Gutala, Mahesh Iyer, Eriko Nurvitadhi, Archanna Srinivasan, Sean Atsatt, James Ball
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Publication number: 20220327271Abstract: Methods and apparatus for extracting a setting of configuration bits to create an exclusion configuration for providing protection against peek and poke attacks in a multi-tenant usage model of a configurable device is provided. The device may host multiple parties that do not trust each other. Peek and poke attacks are orchestrated by tapping (peeking) and driving (poking) wires associated with other parties. Such attacks may be disabled by excluding the settings of configuration bits that would allow these attacks by other parties. This set of configuration bits that should be excluded for preventing all peek and poke attacks creates the exclusion configuration. Methods are described that disable a particular class of peek and/or poke attacks through the use of partial reconfiguration. Methods and apparatus are described to dynamically detect peek and/or poke attacks.Type: ApplicationFiled: June 27, 2022Publication date: October 13, 2022Inventors: Scott Weber, Sean R. Atsatt, David Goldman
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Patent number: 11379645Abstract: Methods and apparatus for extracting a setting of configuration bits to create an exclusion configuration for providing protection against peek and poke attacks in a multi-tenant usage model of a configurable device is provided. The device may host multiple parties that do not trust each other. Peek and poke attacks are orchestrated by tapping (peeking) and driving (poking) wires associated with other parties. Such attacks may be disabled by excluding the settings of configuration bits that would allow these attacks by other parties. This set of configuration bits that should be excluded for preventing all peek and poke attacks creates the exclusion configuration. Methods are described that disable a particular class of peek and/or poke attacks through the use of partial reconfiguration. Methods and apparatus are described to dynamically detect peek and/or poke attacks.Type: GrantFiled: September 28, 2017Date of Patent: July 5, 2022Assignee: Intel CorporationInventors: Scott Weber, Sean R. Atsatt, David Goldman
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Patent number: 11352439Abstract: Modified macrophage immune cells are provided for treatment of cancer and other diseases.Type: GrantFiled: November 22, 2016Date of Patent: June 7, 2022Inventors: Kim Leslie O'Neill, Scott Weber
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Publication number: 20220166124Abstract: An adjustable antenna positioning system feed is disclosed herein. The adjustable antenna positioning system feed includes a feed base, a splash plate assembly, and a feed insert. The feed base is configured to be coupled to a reflector. The splash plate assembly is configured to be removably coupled to the feed base. The adjustable antenna positioning system feed is in a primary arrangement when directly coupled. The feed insert is positioned between the feed base and the splash plate. The adjustable antenna positioning system feed is in a secondary arrangement when the feed insert is coupled with the feed base and the splash plate.Type: ApplicationFiled: November 24, 2021Publication date: May 26, 2022Inventors: Keith Ayotte, Sandeep Palreddy, Scott Weber, Tyler McSorley, Nicholas Keith
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Publication number: 20210330770Abstract: Modified T-cells have paratopes against human TK1 epitopes, are made by producing monoclonal antibodies that are specific to TK1, creating chimeric antigen receptors (CARs) by fusion of the single-chain variable fragments (scFv) of the monoclonal antibodies to T-cell signalling domains, and transducing the CARs to the T-cells.Type: ApplicationFiled: July 2, 2021Publication date: October 28, 2021Inventors: Kim Leslie O'Neill, Scott Weber
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Publication number: 20210313991Abstract: A circuit system includes a first integrated circuit die having a first group of circuits configured to perform a first set of operations. The circuit system also includes a second integrated circuit die having a second group of circuits configured to start performing a second set of operations with a delay after the first group of circuits starts performing the first set of operations to reduce power supply voltage droop. The operations performed by the first and second groups of circuits can be interleaved with a fixed or a variable delay. Logic circuits can be partitioned into the first and the second groups of circuits based on predicted switching activity of the logic circuits. Decoupling capacitors in integrated circuit dies can be coupled together to reduce droop in a supply voltage during a high current event.Type: ApplicationFiled: June 17, 2021Publication date: October 7, 2021Applicant: Intel CorporationInventors: Archanna Srinivasan, Ravi Gutala, Scott Weber, Aravind Dasu, Mahesh Iyer, Eriko Nurvitadhi
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Publication number: 20210311537Abstract: A circuit system includes a power control circuit that generates multiple voltage identifiers. Multiple voltage regulator circuits generate multiple supply voltages based on the voltage identifiers. The supply voltages are provided to multiple integrated circuit dies. The power control circuit varies the voltage identifiers based on changes in metrics associated with the integrated circuit dies to cause the voltage regulator circuits to vary the supply voltages. Integrated circuit dies receive supply voltages from voltage regulator circuits through power delivery networks. The integrated circuit dies provide voltage sense signals that indicates the supply voltages. The voltage regulator circuits adjust the supply voltages based on the voltage sense signals to compensate for voltage drops in the power delivery networks.Type: ApplicationFiled: June 18, 2021Publication date: October 7, 2021Applicant: Intel CorporationInventors: Archanna Srinivasan, Ravi Gutala, Scott Weber, Aravind Dasu, Mahesh Iyer, Eriko Nurvitadhi
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Publication number: 20210311517Abstract: A circuit system includes a first voltage regulator circuit that generates a first supply voltage for an integrated circuit die based on a first control signal. The first voltage regulator circuit generates a first feedback signal based on the first supply voltage. The circuit system also includes a second voltage regulator circuit that generates a second supply voltage for an integrated circuit die based on a second control signal. The second voltage regulator circuit generates a second feedback signal based on the second supply voltage. The circuit system also includes a third voltage regulator circuit that generates the first control signal based on the first feedback signal and the second control signal based on the second feedback signal. The circuit system may include fully integrated, on-board, and on-package voltage regulator circuits.Type: ApplicationFiled: June 18, 2021Publication date: October 7, 2021Applicant: Intel CorporationInventors: Archanna Srinivasan, Ravi Gutala, Scott Weber, Aravind Dasu, Mahesh Iyer, Eriko Nurvitadhi
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Publication number: 20210313988Abstract: A three dimensional circuit system includes first and second integrated circuit (IC) dies. The first IC die includes programmable logic circuits arranged in sectors and first programmable interconnection circuits having first router circuits. The second IC die includes non-programmable circuits arranged in regions and second programmable interconnection circuits having second router circuits. Each of the regions in the second IC die is vertically aligned with at least one of the sectors in the first IC die. Each of the second router circuits is coupled to one of the first router circuits through a vertical die-to-die connection. The first and second programmable interconnection circuits are programmable to route signals between the programmable logic circuits and the non-programmable circuits through the first and second router circuits. The circuit system may include additional IC dies. The first and second IC dies and any additional IC dies are coupled in a vertically stacked configuration.Type: ApplicationFiled: June 22, 2021Publication date: October 7, 2021Applicant: Intel CorporationInventors: Scott Weber, Aravind Dasu, Ravi Gutala, Mahesh Iyer, Eriko Nurvitadhi, Archanna Srinivasan, Sean Atsatt, James Ball
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Patent number: 11052138Abstract: A nucleic acid encoding a chimeric antigen receptor (CAR) comprising a single-chain variable fragment (scFv) operatively linked to a signaling domain that polarizes a macrophage to an M1 macrophage; wherein the nucleic acid is operatively linked to a macrophage specific promoter; and wherein the scFv is specific for a human antigen. Monocytes or macrophages comprising such a nucleic acid.Type: GrantFiled: September 5, 2018Date of Patent: July 6, 2021Assignee: Thunder Biotech Inc.Inventors: Kim Leslie O'Neill, Scott Weber