Abstract: A signal distribution architecture for clock and reset signal distribution in a programmable array is disclosed. The architecture includes separate networks for distributing clock and reset signals to logic cells of the array. Each network includes a plurality of column multiplexers for selecting a column clock or reset signal from a plurality of system clock or reset signals. Within each column of logic cells are positioned sector multiplexers for selecting a sector clock or reset signal from a plurality of column clock or reset signals. The clock and reset signals are applied to the combinatorial and sequential logic circuits of each logic cell associated with a given sector multiplexer. A clock gate circuit is controlled cooperatively with an output multiplexer in each logic cell. The networks are designed with features to minimize signal skew including signal source buffering, multiplexer signal buffering and output driver sizing as a function of signal propagation distance.

Abstract: A signal distribution architecture for clock and reset signal distribution in a programmable array is disclosed. The architecture includes separate networks for distributing clock and reset signals to logic cells of the array. Each network includes a plurality of column multiplexers for selecting a column clock or reset signal from a plurality of system clock or reset signals. Within each column of logic cells are positioned sector multiplexers for selecting a sector clock or reset signal from a plurality of column clock or reset signals. The clock and reset signals are applied to the combinatorial and sequential logic circuits of each logic cell associated with a given sector multiplexer. A clock gate circuit is controlled cooperatively with an output multiplexer in each logic cell. The networks are designed with features to minimize signal skew including signal source buffering, multiplexer signal buffering and output driver sizing as a function of signal propagation distance.

Abstract: In a programmable gate array ("PGA"), logic cells therein are programmed to create a combined output with enhanced current driving ability. Specifically, a first logic cell is programmed to have a first output and a second logic cell is programmed to have a second output. The first and second outputs are connected within the PGA forming a combined output having enhanced current driving ability by the first logic cell and the second logic cell. The first and second logic cells are programmed with identical logic functions such that they operate in parallel.

Abstract: A programmable array having programmable logic cells, a programmable interconnect network and a programmable I/O system. Two I/O interfaces are provided for respective logic cells about the perimeter of the array. The I/O interfaces comprise input, output and enable paths. Each of these paths has an associated multiplexer. An I/O routing network is positioned about the perimeter of the array. Conductors connecting the I/O interface multiplexers to the programmable interconnect network also intersect, and can be programmably connected to, buses of the I/O routing network.

Abstract: A signal distribution architecture for clock and reset signal distribution in a programmable array is disclosed. The architecture includes separate networks for distributing clock and reset signals to logic cells of the array. Each network includes a plurality of column multiplexers for selecting a column clock or reset signal from a plurality of system clock or reset signals. Within each column of logic cells are positioned sector multiplexers for selecting a sector clock or reset signal from a plurality of column clock or reset signals. The clock and reset signals are applied to the combinatorial and sequential logic circuits of each logic cell associated with a given sector multiplexer. A clock gate circuit is controlled cooperatively with an output multiplexer in each logic cell. The networks are designed with features to minimize signal skew including signal source buffering, multiplexer signal buffering, and output driver sizing as a function of signal propagation distance.

Abstract: A programmable logic cell has four logic gates, two of which are configurable. The two configurable logic gates are positioned near the logic cell inputs. Each configurable logic gate has two inputs, each input being connected to one of the four logic cell inputs. The remaining two logic gates receive the outputs of the configurable logic gates. Four independent logic cell input nodes are provided, each having associated therewith a programmable input multiplexer. Each input multiplexer can have inputs connected to at least two types of interconnect conductors. The cell also has two output paths, each having associated therewith an independently-controlled output multiplexer. The output of each output multiplexer is connected to an input of the other output multiplexer. Additional features include a multiplexer having inputs connected to two cell input nodes, a select input connected to a third logic cell input node, and an output connected to a cell output node; a system low-skew data (e.g.

Abstract: A liquid purification system capable of separating a first liquid from a second liquid, in which the first liquid is a corrosive aqueous liquid that is wholly or partly immiscible in and forms a discontinuous phase with a second, continuous phase-forming organic liquid is provided including a housing, a fluid inlet in the housing, a first liquid outlet in the housing, a second liquid outlet in the housing, at least one coalescing assembly for coalescing the first liquid, and a liquid separating region in the housing. The coalescing assembly has at least one coalescing element which includes a halocarbon polymer packing material having a solid capture efficiency of as high as 20 .mu.m, is substantially chemically inert to corrosive liquids and is adapted to separate liquids differing in interfacial tension of at least about 0.6 dynes/cm.

Abstract: A liquid purification system is provided which is capable of separating a first liquid, that is wholly or partly immiscible in and forms a discontinuous phase with a second, continuous phase-forming liquid, from the second liquid, which includes at least one coalescing element or assembly for coalescing the first liquid having at least one fluid inlet at the top thereof; and at least one separating element or assembly for separating droplets of the first liquid from the second liquid, the at least one coalescing element or assembly being arranged in superposed and fluid communicable relationship above the at least one separating element or assembly