Abstract: Embodiments include systems and methods for integration of RF components onto a single die with functional processing circuitry. For example, one integrated circuit may comprise multiple processors that can communicate there between by way of Radio Frequency (RF) transmission. The processors may also communicate with slave devices by way of radio frequency. Transmission and reception may be at frequencies in a band hitherto unused in computing devices and their peripherals.

Abstract: Apparatus, system, and method for multi-class wireless receiver are described. The multi-class receiver includes a first down-converter coupled to an input port, a filter coupled to the first-down converter, and a second down-converter coupled to the filter. In a first mode, the filter is configured as a first filter and the second down-converter is disabled. In a second mode, the filter is configured as a second filter and the second down converter is enabled. The system includes a wireless module and a wireless transceiver in communication with the wireless module. The method includes receiving multi-class RF signals, converting at least a first class of RF signals in a first mode of operation, and converting at least a second class of RF signals in a second mode of operation with said multi-class receiver.

Abstract: A timing recovery system includes a phase locked loop with a variable bandwidth loop filter, several data dependent gain units, and three proportional paths with non-linear control. The system provides excellent jitter tolerance with a wide variation in data density and large amplitude jitter with a wide frequency range. The gain of both an included loop filter and a phase detector may be varied with both frequency and data density. Direct, unfiltered adjustments may be made to phase based on a received data pattern and phase error magnitude to reduce loop latency and provide temporary and immediate boost in the loop gain of the phase locked loop. Direct, unfiltered adjustments may also be made to phase based on the sign of the first differential of an accumulator output during long strings of zeros to help maintain tracking even with a very low data density.

Abstract: A receiver involved in high-speed data transmission includes a decision system. The decision system calculates a value of an input signal and holds the value as a tentative value. The decision system calculates an error value, amplifies the error value, and holds the amplified error value as a corrected value. The decision system determines whether the amplified error value is within a marginal range. The decision system also determines whether adjacent values to the value indicate the input signal was in transition from a positive to negative state, or a negative to positive state. If the amplified error values is within a marginal range and the input signal was in transition from a positive to negative state, or a negative to positive state, then the decision system overrides the tentative value with the corrected value.

Abstract: In some embodiments, an apparatus includes a line side circuit and a system side circuit to couple to the line side circuit via an isolation interface. The system side circuit includes a first clock line to couple to the line side circuit via a first capacitor to supply a first clock signal to the line side circuit, and a second clock line to couple to the line side circuit via a second capacitor to supply a second clock signal to the line side circuit.

Abstract: Briefly, a finite impulse response filter to generating coefficients having a programmable magnitude and quantum tunability.

Abstract: One embodiment of the invention provides a method, system, and apparatus to update an adaptive filter real-time based on pre-determined filter configurations. When it is determined that an adaptive filter should be updated, a request is made for an updated filter configuration. An updated filter configuration is provided from a storage device that stores multiple pre-determined filter configurations for various operating conditions.

Abstract: A frequency detector includes a slicer to receive and slice a phase error against a compare threshold value. The slicer generates a symbol based on the phase error sliced against the compare threshold value. A symbol counter is provided to increment a symbol count if the symbol generated is the same as a last symbol. A logic circuit compares the symbol count with a symbol count limit if the symbol is different from the last symbol. The logic circuit increments a high counter and clears a low counter if the symbol count is less than the symbol count limit. The logic circuit increments the low counter and clears the high counter if the symbol count is greater than the symbol count limit. A combinational logic circuit is provided to generate a high frequency jitter true signal or a high frequency jitter false signal based on at least one of the symbol count, the high counter, and the low counter.

Abstract: A receiver involved in high-speed data transmission includes a decision system. The decision system calculates a value of an input signal and holds the value as a tentative value. The decision system calculates an error value, amplifies the error value, and holds the amplified error value as a corrected value. The decision system determines whether the amplified error value is within a marginal range. The decision system also determines whether adjacent values to the value indicate the input signal was in transition from a positive to negative state, or a negative to positive state. If the amplified error values is within a marginal range and the input signal was in transition from a positive to negative state, or a negative to positive state, then the decision system overrides the tentative value with the corrected value.

Abstract: A timing recovery system includes a phase locked loop with a variable bandwidth loop filter, several data dependent gain units, and three proportional paths with non-linear control. The system provides excellent jitter tolerance with a wide variation in data density and large amplitude jitter with a wide frequency range. The gain of both an included loop filter and a phase detector may be varied with both frequency and data density. Direct, unfiltered adjustments may be made to phase based on a received data pattern and phase error magnitude to reduce loop latency and provide temporary and immediate boost in the loop gain of the phase locked loop. Direct, unfiltered adjustments may also be made to phase based on the sign of the first differential of an accumulator output during long strings of zeros to help maintain tracking even with a very low data density.

Abstract: A frequency detector includes a slicer to receive and slice a phase error against a compare threshold value. The slicer generates a symbol based on the phase error sliced against the compare threshold value. A symbol counter is provided to increment a symbol count if the symbol generated is the same as a last symbol. A logic circuit compares the symbol count with a symbol count limit if the symbol is different from the last symbol. The logic circuit increments a high counter and clears a low counter if the symbol count is less than the symbol count limit. The logic circuit increments the low counter and clears the high counter if the symbol count is greater than the symbol count limit. A combinational logic circuit is provided to generate a high frequency jitter true signal or a high frequency jitter false signal based on at least one of the symbol count, the high counter, and the low counter.

Abstract: A display driver circuit having graphics and bilevel modes drives a display (110). A column control circuit (112) includes a shift register (302) with display blanking and bi-directional shifting for scanning the display (110) in either direction for driving display (110) from either end. A dual mode row driver (502) provides graphics capability for displaying images and low power operation when displaying text. In graphics mode, a four-bit luminance word controls a row drive pulse to produce a representative pixel brightness in the display (110). In bilevel mode, the system clock (VCLOCK) is reduced in frequency to conserve power while maintaining data transfer and refresh rates.

Abstract: A method and apparatus includes row-major memory mapping for a graphics memory (14) while providing data to a column-major display such as a pixel array (19). The transfer of data is provided from a row-major memory map to data formatted for refreshing a column-major display. The column-major pixel array (19) provides a display with energy saving benefits for illuminating the LEDs. A software developer can provide graphics data generated or transferred by a microcontroller (12) for storage in the row-major graphics memory (14). The embodiment supports the display features such as the grey-scale mode and bi-level mode.

Abstract: A display controller (112) reduces the power consumed in displaying a graphics image in a portable wireless communications device (100) when a graphics image is smaller than the size of the display (118). The number of rows and columns used to display the graphics image is counted by a decoder (108) which is a microcontroller used to operate the communications device (100). The decoder (108) provides the reduced row or column count to the display controller (112), which reduces the frequencies of clocks (PIXEL CLOCK, LINE PULSE, FRAME PULSE) used for timing data transfers to the display (118). Power is reduced by operating the display (118) at a lower frequency while acceptable frame refresh rates are maintained.