Patents by Inventor Scott D. Hahn
Scott D. Hahn has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20200250003Abstract: In one embodiment, an apparatus comprises a processor to: identify a workload comprising a plurality of tasks; generate a workload graph based on the workload, wherein the workload graph comprises information associated with the plurality of tasks; identify a device connectivity graph, wherein the device connectivity graph comprises device connectivity information associated with a plurality of processing devices; identify a privacy policy associated with the workload; identify privacy level information associated with the plurality of processing devices; identify a privacy constraint based on the privacy policy and the privacy level information; and determine a workload schedule, wherein the workload schedule comprises a mapping of the workload onto the plurality of processing devices, and wherein the workload schedule is determined based on the privacy constraint, the workload graph, and the device connectivity graph.Type: ApplicationFiled: June 29, 2018Publication date: August 6, 2020Applicant: Intel CorporationInventors: Shao-Wen Yang, Yen-Kuang Chen, Ragaad Mohammed Irsehid Altarawneh, Juan Pablo Munoz Chiabrando, Siew Wen Chin, Kushal Datta, Subramanya R. Dulloor, Julio C. Zamora Esquivel, Omar Ulises Florez Choque, Vishakha Gupta, Scott D. Hahn, Rameshkumar Illikkal, Nilesh Kumar Jain, Siti Khairuni Amalina Kamarol, Anil S. Keshavamurthy, Heng Kar Lau, Jonathan A. Lefman, Yiting Liao, Michael G. Millsap, Ibrahima J. Ndiour, Luis Carlos Maria Remis, Addicam V. Sanjay, Usman Sarwar, Eve M. Schooler, Ned M. Smith, Vallabhajosyula S. Somayazulu, Christina R. Strong, Omesh Tickoo, Srenivas Varadarajan, Jesús A. Cruz Vargas, Hassnaa Moustafa, Arun Raghunath, Katalin Klara Bartfai-Walcott, Maruti Gupta Hyde, Deepak S. Vembar, Jessica McCarthy
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Patent number: 10503517Abstract: A heterogeneous processor architecture and a method of booting a heterogeneous processor is described. A processor according to one embodiment comprises: a set of large physical processor cores; a set of small physical processor cores having relatively lower performance processing capabilities and relatively lower power usage relative to the large physical processor cores; and a package unit, to enable a bootstrap processor. The bootstrap processor initializes the homogeneous physical processor cores, while the heterogeneous processor presents the appearance of a homogeneous processor to a system firmware interface.Type: GrantFiled: August 8, 2017Date of Patent: December 10, 2019Assignee: Intel CorporationInventors: Eliezer Weissmann, Rinat Rappoport, Michael Mishaeli, Hisham Shafi, Oron Lenz, Jason W. Brandt, Stephen A. Fischer, Bret L. Toll, Inder M. Sodhi, Alon Naveh, Ganapati N. Srinivasa, Ashish V. Choubal, Scott D. Hahn, David A. Koufaty, Russel J. Fenger, Gaurav Khanna, Eugene Gorbatov, Mishali Naik, Andrew J. Herdrich, Abirami Prabhakaran, Sanjeev S. Sahagirdar, Paul Brett, Paolo Narvaez, Andrew D. Henroid, Dheeraj R. Subbareddy
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Patent number: 10313256Abstract: Embodiments of apparatuses and methods for adaptive data compression and associated contextual information are described. In various embodiments, an apparatus may include a context monitoring module to gather contextual information for transmission of data and a policy module to gather user preference on cost associated with transmission of data. The apparatus may further include an analysis module to determine whether to compress data prior to transmission, based at least in part on the contextual information and the user preference. Other embodiments may be described and/or claimed.Type: GrantFiled: May 21, 2015Date of Patent: June 4, 2019Assignee: Intel CorporationInventors: Ren Wang, Weishuang Zhao, Alexander W. Min, Michael P. Mesnier, Richard Chuang, Tsung-Yuan C. Tai, Scott D. Hahn
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Patent number: 10185566Abstract: In one embodiment, the present invention includes a multicore processor having first and second cores to independently execute instructions, the first core visible to an operating system (OS) and the second core transparent to the OS and heterogeneous from the first core. A task controller, which may be included in or coupled to the multicore processor, can cause dynamic migration of a first process scheduled by the OS to the first core to the second core transparently to the OS. Other embodiments are described and claimed.Type: GrantFiled: April 27, 2012Date of Patent: January 22, 2019Assignee: Intel CorporationInventors: Alon Naveh, Yuval Yosef, Eliezer Weissmann, Anil Aggarwal, Efraim Rotem, Avi Mendelson, Ronny Ronen, Boris Ginzburg, Michael Mishaeli, Scott D. Hahn, David A. Koufaty, Ganapati Srinivasa, Guy Therien
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Publication number: 20180060078Abstract: A heterogeneous processor architecture and a method of booting a heterogeneous processor is described. A processor according to one embodiment comprises: a set of large physical processor cores; a set of small physical processor cores having relatively lower performance processing capabilities and relatively lower power usage relative to the large physical processor cores; and a package unit, to enable a bootstrap processor. The bootstrap processor initializes the homogeneous physical processor cores, while the heterogeneous processor presents the appearance of a homogeneous processor to a system firmware interface.Type: ApplicationFiled: August 8, 2017Publication date: March 1, 2018Inventors: Eliezer Weissmann, Rinat Rappoport, Michael Mishaeli, Hisham Shafi, Oron Lenz, Jason W. Brandt, Stephen A. Fischer, Bret L. Toll, Inder M. Sodhi, Alon Naveh, Ganapati N. Srinivasa, Ashish V, Choubal, Scott D. Hahn, David A. Koufaty, Russel J. Fenger, Gaurav Khanna, Eugene Gorbatov, Mishali Naik, Andrew J. Herdrich, Abirami Prabhakaran, Sanjeev S. Sahagirdar, Paul Brett, Paolo Narvaez, Andrew D. Henroid, Dheeraj R. Subbareddy
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Patent number: 9727345Abstract: A heterogeneous processor architecture and a method of booting a heterogeneous processor is described. A processor according to one embodiment comprises: a set of large physical processor cores; a set of small physical processor cores having relatively lower performance processing capabilities and relatively lower power usage relative to the large physical processor cores; and a package unit, to enable a bootstrap processor. The bootstrap processor initializes the homogeneous physical processor cores, while the heterogeneous processor presents the appearance of a homogeneous processor to a system firmware interface.Type: GrantFiled: March 29, 2013Date of Patent: August 8, 2017Assignee: Intel CorporationInventors: Eliezer Weissmann, Rinat Rappoport, Michael Mishaeli, Hisham Shafi, Oron Lenz, Jason W. Brandt, Stephen A. Fischer, Bret L. Toll, Inder M. Sodhi, Alon Naveh, Ganapati N. Srinivasa, Ashish V. Choubal, Scott D. Hahn, David A. Koufaty, Russell J. Fenger, Gaurav Khanna, Eugene Gorbatov, Mishali Naik, Andrew J. Herdrich, Abirami Prabhakaran, Sanjeev S. Sahagirdar, Paul Brett, Paolo Narvaez, Andrew D. Henroid, Dheeraj R. Subbareddy
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Patent number: 9720730Abstract: In one embodiment, the present invention includes a multicore processor with first and second groups of cores. The second group can be of a different instruction set architecture (ISA) than the first group or of the same ISA set but having different power and performance support level, and is transparent to an operating system (OS). The processor further includes a migration unit that handles migration requests for a number of different scenarios and causes a context switch to dynamically migrate a process from the second core to a first core of the first group. This dynamic hardware-based context switch can be transparent to the OS. Other embodiments are described and claimed.Type: GrantFiled: December 30, 2011Date of Patent: August 1, 2017Assignee: Intel CorporationInventors: Boris Ginzburg, Ilya Osadchiy, Ronny Ronen, Eliezer Weissmann, Michael Mishaeli, Alon Naveh, David A. Koufaty, Scott D. Hahn, Tong Li, Avi Mendleson, Eugene Gorbatov, Hisham Abu-Salah, Dheeraj R. Subbareddy, Paolo Narvaez, Aamer Jaleel, Efraim Rotem, Yuval Yosef, Anil Aggarwal, Kenzo Van Craeynest
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Patent number: 9703562Abstract: A processor of an aspect includes decode logic to receive a first instruction and to determine that the first instruction is to be emulated. The processor also includes emulation mode aware post-decode instruction processor logic coupled with the decode logic. The emulation mode aware post-decode instruction processor logic is to process one or more control signals decoded from an instruction. The instruction is one of a set of one or more instructions used to emulate the first instruction. The one or more control signals are to be processed differently by the emulation mode aware post-decode instruction processor logic when in an emulation mode than when not in the emulation mode. Other apparatus are also disclosed as well as methods and systems.Type: GrantFiled: March 16, 2013Date of Patent: July 11, 2017Assignee: Intel CorporationInventors: William C. Rash, Bret L. Toll, Scott D. Hahn, Glenn J. Hinton
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Patent number: 9672046Abstract: An intelligent power allocation architecture for a processor. For example, one embodiment of a processor comprises: a plurality of processor components for performing a corresponding plurality of processor functions; a plurality of power planes, each power plane associated with one of the processor components; and a power control unit (PCU) to dynamically adjust power to each of the power planes based on user experience metrics, workload characteristics, and power constraints for a current use of the processor.Type: GrantFiled: December 28, 2012Date of Patent: June 6, 2017Assignee: Intel CorporationInventors: Dheeraj R. Subbareddy, Ganapati N. Srinivasa, Eugene Gorbatov, Scott D. Hahn, David A. Koufaty, Paul Brett, Abirami Prabhakaran
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Patent number: 9639372Abstract: A heterogeneous processor architecture is described. For example, a processor according to one embodiment of the invention comprises: a set of large physical processor cores; a set of small physical processor cores having relatively lower performance processing capabilities and relatively lower power usage relative to the large physical processor cores; virtual-to-physical (V-P) mapping logic to expose the set of large physical processor cores to software through a corresponding set of virtual cores and to hide the set of small physical processor core from the software.Type: GrantFiled: December 28, 2012Date of Patent: May 2, 2017Assignee: INTEL CORPORATIONInventors: Paolo Narvaez, Ganapati N. Srinivasa, Eugene Gorbatov, Dheeraj R. Subbareddy, Mishali Naik, Alon Naveh, Abirami Prabhakaran, Eliezer Weissmann, David A. Koufaty, Paul Brett, Scott D. Hahn, Andrew J. Herdrich, Ravishankar Iyer, Nagabhushan Chitlur, Inder M. Sodhi, Gaurav Khanna, Russell J. Fenger
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Publication number: 20160344646Abstract: Embodiments of apparatuses and methods for adaptive data compression and associated contextual information are described. In various embodiments, an apparatus may include a context monitoring module to gather contextual information for transmission of data and a policy module to gather user preference on cost associated with transmission of data. The apparatus may further include an analysis module to determine whether to compress data prior to transmission, based at least in part on the contextual information and the user preference. Other embodiments may be described and/or claimed.Type: ApplicationFiled: May 21, 2015Publication date: November 24, 2016Inventors: Ren Wang, Weishuang Zhao, Alexander W. Min, Michael P. Mesnier, Richard Chuang, Tsung-Yuan C. Tai, Scott D. Hahn
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Patent number: 9448829Abstract: A heterogeneous processor architecture is described. For example, a processor according to one embodiment of the invention comprises: a set of two or more small physical processor cores; at least one large physical processor core having relatively higher performance processing capabilities and relatively higher power usage relative to the small physical processor cores; virtual-to-physical (V-P) mapping logic to expose the set of two or more small physical processor cores to software through a corresponding set of virtual cores and to hide the at least one large physical processor core from the software.Type: GrantFiled: December 28, 2012Date of Patent: September 20, 2016Assignee: INTEL CORPORATIONInventors: Paolo Narvaez, Ganapati N. Srinivasa, Eugene Gorbatov, Dheeraj R. Subbareddy, Mishali Naik, Alon Naveh, Abirami Prabhakaran, Eliezer Weissmann, Paul Brett, Scott D. Hahn, Andrew J. Herdrich, Gaurav Khanna, Russell J. Fenger, Bryant E. Bigbee, Andrew D. Henroid, David A. Koufaty
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Patent number: 9329900Abstract: A heterogeneous processor architecture is described.Type: GrantFiled: December 28, 2012Date of Patent: May 3, 2016Assignee: INTEL CORPORATIONInventors: Paolo Narvaez, Ganapati N. Srinivasa, Eugene Gorbatov, Dheeraj R. Subbareddy, Mishali Naik, Alon Naveh, Abirami Prabhakaran, Eliezer Weissmann, David A. Koufaty, Paul Brett, Scott D. Hahn, Andrew J. Herdrich, Ravishankar Iyer, Nagabhushan Chitlur, Inder M. Sodhi, Gaurav Khanna, Russell J. Fenger
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Publication number: 20150095614Abstract: An apparatus and method are described for the efficient migration of architectural state between processor cores. For example, a processor according to one embodiment comprises: a first processing core having a first instruction execution pipeline including first register set for storing a first architectural state of a first thread being executed thereon; a second processing core having a second instruction execution pipeline including a second register set for storing a second architectural state of a second thread being executed thereon; and architectural state migration logic to perform a direct, simultaneous swap of the first architectural state from the first register set with the second architectural state from the second register set responsive to detecting that the execution of the first thread is to be migrated from the first core to the second core.Type: ApplicationFiled: September 27, 2013Publication date: April 2, 2015Inventors: Bret L. Toll, Scott D. Hahn, Jason W. Brandt, Thomas F. Toll
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Publication number: 20140281457Abstract: A heterogeneous processor architecture and a method of booting a heterogeneous processor is described. A processor according to one embodiment comprises: a set of large physical processor cores; a set of small physical processor cores having relatively lower performance processing capabilities and relatively lower power usage relative to the large physical processor cores; and a package unit, to enable a bootstrap processor. The bootstrap processor initializes the homogeneous physical processor cores, while the heterogeneous processor presents the appearance of a homogeneous processor to a system firmware interface.Type: ApplicationFiled: March 29, 2013Publication date: September 18, 2014Inventors: Elierzer Weissmann, Rinat Rappoport, Michael Mishaeli, Hisham Shafi, Oron Lenz, Jason W. Brandt, Stephen A. Fischer, Bret L. Toll, Inder M. Sodhi, Alon Naveh, Ganapati N. Srinivasa, Ashish V. Choubal, Scott D. Hahn, David A. Koufaty, Russel J. Fenger, Gaurav Khanna, Eugene Gorbatov, Mishali Naik, Andrew J. Herdrich, Abirami Prabhakaran, Sanjeev S. Sahagirdar, Paul Brett, Paolo Narvaez, Andrew D. Henroid, Dheeraj R. Subbareddy
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Publication number: 20140281399Abstract: A processor of an aspect includes decode logic to receive a first instruction and to determine that the first instruction is to be emulated. The processor also includes emulation mode aware post-decode instruction processor logic coupled with the decode logic. The emulation mode aware post-decode instruction processor logic is to process one or more control signals decoded from an instruction. The instruction is one of a set of one or more instructions used to emulate the first instruction. The one or more control signals are to be processed differently by the emulation mode aware post-decode instruction processor logic when in an emulation mode than when not in the emulation mode. Other apparatus are also disclosed as well as methods and systems.Type: ApplicationFiled: March 16, 2013Publication date: September 18, 2014Inventors: WILLIAM C. RASH, BRET L. TOLL, SCOTT D. HAHN, GLENN J. HINTON
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Publication number: 20140281236Abstract: Systems and methods for implementing transactional memory access. An example method may comprise initiating a memory access transaction; executing a transactional read operation, using a first buffer associated with a memory access tracking logic, with respect to a first memory location, and/or a transactional write operation, using a second buffer associated with the memory access tracking logic, with respect to a second memory location; executing a non-transactional read operation with respect to a third memory location, and/or a non-transactional write operation with respect to a fourth memory location; responsive to detecting, by the memory access tracking logic, access by a device other than the processor to the first memory location or the second memory location, aborting the memory access transaction; and completing, irrespectively of the state of the third memory location and the fourth memory location, the memory access transaction responsive to failing to detect a transaction aborting condition.Type: ApplicationFiled: March 14, 2013Publication date: September 18, 2014Inventors: William C. Rash, Scott D. Hahn, Bret L. Toll, Glenn J. Hinton
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Publication number: 20140189299Abstract: A heterogeneous processor architecture is described. For example, a processor according to one embodiment of the invention comprises: a set of large physical processor cores; a set of small physical processor cores having relatively lower performance processing capabilities and relatively lower power usage relative to the large physical processor cores; virtual-to-physical (V-P) mapping logic to expose the set of large physical processor cores to software through a corresponding set of virtual cores and to hide the set of small physical processor core from the software.Type: ApplicationFiled: December 28, 2012Publication date: July 3, 2014Inventors: Paolo Narvaez, Ganapati N. Srinivasa, Eugene Gorbatov, Dheeraj R. Subbareddy, Mishali Naik, Alon Naveh, Abirami Prabhakaran, Eliezer Weissmann, David A. Koufaty, Paul Brett, Scott D. Hahn, Andrew J. Herdrich, Ravishankar Iyer, Nagabhushan Chitlur, Inder M. Sodhi, Gaurav Khanna, Russell J. Fenger
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Publication number: 20140189704Abstract: A heterogeneous processor architecture is described.Type: ApplicationFiled: December 28, 2012Publication date: July 3, 2014Inventors: Paolo Narvaez, Ganapati N. Srinivasa, Eugene Gorbatov, Dheeraj R. Subbareddy, Mishali Naik, Alon Naveh, Abirami Prabhakaran, Eliezer Weissmann, David A. Koufaty, Paul Brett, Scott D. Hahn, Andrew J. Herdrich, Ravishankar Iyer, Nagabhushan Chitlur, Inder M. Sodhi, Gaurav Khanna, Russell J. Fenger
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Publication number: 20140189377Abstract: An intelligent power allocation architecture for a processor. For example, one embodiment of a processor comprises: a plurality of processor components for performing a corresponding plurality of processor functions; a plurality of power planes, each power plane associated with one of the processor components; and a power control unit (PCU) to dynamically adjust power to each of the power planes based on user experience metrics, workload characteristics, and power constraints for a current use of the processor.Type: ApplicationFiled: December 28, 2012Publication date: July 3, 2014Inventors: Dheeraj R. Subbareddy, Ganapati N. Srinivasa, Eugene Gorbatov, Scott D. Hahn, David A. Koufaty, Paul Brett, Abirami Prabhakaran