Abstract: A heterogeneous processor architecture is described. For example, a processor according to one embodiment of the invention comprises: a set of two or more small physical processor cores; at least one large physical processor core having relatively higher performance processing capabilities and relatively higher power usage relative to the small physical processor cores; virtual-to-physical (V-P) mapping logic to expose the set of two or more small physical processor cores to software through a corresponding set of virtual cores and to hide the at least one large physical processor core from the software.

Abstract: A heterogeneous processor architecture is described.

Abstract: According to one embodiment, a processor includes a plurality of processor cores for executing a plurality of threads, a shared storage communicatively coupled to the plurality of processor cores, a power control unit (PCU) communicatively coupled to the plurality of processors to determine, without any software (SW) intervention, if a thread being performed by a first processor core should be migrated to a second processor core, and a migration unit, in response to receiving an instruction from the PCU to migrate the thread, to store at least a portion of architectural state of the first processor core in the shared storage and to migrate the thread to the second processor core, without any SW intervention, such that the second processor core can continue executing the thread based on the architectural state from the shared storage without knowledge of the SW.

Abstract: In one embodiment, the present invention includes a multicore processor having first and second cores to independently execute instructions, the first core visible to an operating system (OS) and the second core transparent to the OS and heterogeneous from the first core. A task controller, which may be included in or coupled to the multicore processor, can cause dynamic migration of a first process scheduled by the OS to the first core to the second core transparently to the OS. Other embodiments are described and claimed.

Abstract: In one embodiment, the present invention includes a multicore processor with first and second groups of cores. The second group can be of a different instruction set architecture (ISA) than the first group or of the same ISA set but having different power and performance support level, and is transparent to an operating system (OS). The processor further includes a migration unit that handles migration requests for a number of different scenarios and causes a context switch to dynamically migrate a process from the second core to a first core of the first group. This dynamic hardware-based context switch can be transparent to the OS. Other embodiments are described and claimed.

Abstract: An embodiment of the present invention provides an apparatus, comprising an RFID tag interfaced with the apparatus, the RFID tag enables wireless provisioning and configuration of the apparatus and may be a passive read/write RFID tag. The apparatus may be, in one embodiment, a platform such as a client or server and the passive RFID tag may be interfaced with the platform such that the tag's EEPROM can also be read from or written to by the platform using a wired serial connection. The apparatus may further comprise a host processor with an operating system (OS) and an embedded microcontroller, the embedded microcontroller may have access to dynamic and non-volatile memory capable of operating independently of the host processor and OS and with direct access to a network interface, wherein the RFID tag may be read from or written to by either a RFID reader or the platform via a direct connection to the embedded processor.

Abstract: Policy rules are disseminated on a network and are received by one or more devices on the network. Each device is configured with a proxy agent that translates the policy data into a format that is meaningful to the device. The agent translates the policy rules into an access list that generates permit and deny filters that determine the access that the device is allowed on the network.

Abstract: An electrical conductor having an adjustable length is provided comprising a first conducting segment, a second conducting segment, and at least one conducting extension having a first end and a second end. The electrical conductor can be configured in a first configuration such that the first conducting segment is directly connected to the second conducting segment, and can be configured in a second configuration such that the first conducting segment is connected to the first end of the at least one conducting extension and the second conducting segment is connected to the second end of the at least one conducting extension.