Patents by Inventor Scott E. Meninger
Scott E. Meninger has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11757609Abstract: A circuit and method enables multiple serializer/deserializer (SerDes) data lanes of a physical layer device (PHY) to operate across a broad range of diversified data rates that are independent from lane to lane. The multiple SerDes data lanes may operate at data rates independent from one another. A single low frequency clock is input to the PHY. A frequency of the single low frequency clock is increased via a common integer-N phase-locked loop (PLL) on the PHY to produce a higher frequency clock. Each of the SerDes data lanes is operated, independently, as a fractional-N PLL that employs the higher frequency clock. Use of the common integer-N PLL enables modulation noise of the fractional-N PLLs to be suppressed by moving the modulation noise to higher frequencies where a level of the modulation noise is filtered, avoiding use of high risk noise cancellation techniques.Type: GrantFiled: May 18, 2021Date of Patent: September 12, 2023Assignee: Marvell Asia Pte, Ltd.Inventor: Scott E. Meninger
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Publication number: 20210273776Abstract: A circuit and method enables multiple serializer/deserializer (SerDes) data lanes of a physical layer device (PHY) to operate across a broad range of diversified data rates that are independent from lane to lane. The multiple SerDes data lanes may operate at data rates independent from one another. A single low frequency clock is input to the PHY. A frequency of the single low frequency clock is increased via a common integer-N phase-locked loop (PLL) on the PHY to produce a higher frequency clock. Each of the SerDes data lanes is operated, independently, as a fractional-N PLL that employs the higher frequency clock. Use of the common integer-N PLL enables modulation noise of the fractional-N PLLs to be suppressed by moving the modulation noise to higher frequencies where a level of the modulation noise is filtered, avoiding use of high risk noise cancellation techniques.Type: ApplicationFiled: May 18, 2021Publication date: September 2, 2021Inventor: Scott E. Meninger
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Patent number: 11044071Abstract: A circuit and method enables multiple serializer/deserializer (SerDes) data lanes of a physical layer device (PHY) to operate across a broad range of diversified data rates that are independent from lane to lane. The multiple SerDes data lanes may operate at data rates independent from one another. A single low frequency clock is input to the PHY. A frequency of the single low frequency clock is increased via a common integer-N phase-locked loop (PLL) on the PHY to produce a higher frequency clock. Each of the SerDes data lanes is operated, independently, as a fractional-N PLL that employs the higher frequency clock. Use of the common integer-N PLL enables modulation noise of the fractional-N PLLs to be suppressed by moving the modulation noise to higher frequencies where a level of the modulation noise is filtered, avoiding use of high risk noise cancellation techniques.Type: GrantFiled: September 12, 2019Date of Patent: June 22, 2021Assignee: Marvell Asia Pte, Ltd.Inventor: Scott E. Meninger
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Patent number: 10615746Abstract: A method and apparatus select an optimal frequency band of a plurality of frequency bands of a multi-band voltage-controlled oscillator (VCO) to achieve a particular output frequency from the multi-band VCO. The optimal frequency band is selected, automatically, based on performing a one-point calibration phase followed by a multi-point calibration phase. The one-point calibration phase produces an initial frequency band selection and the multi-point calibration phase selects the optimal frequency band from a group of frequency bands including the initial frequency band selection, a higher frequency band consecutively higher in frequency relative to the initial frequency band selection, and a lower frequency band consecutively lower in frequency relative to the initial frequency band selection.Type: GrantFiled: November 29, 2017Date of Patent: April 7, 2020Assignee: Cavium, LLCInventors: Omer O. Yildirim, JingDong Deng, Scott E. Meninger
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Patent number: 10536257Abstract: In some embodiments, the circuits (and methods) may include a reference generator configured to generate a reference signal. The circuits (and methods) may also include a signal presence detection module configured to perform calibration on itself, during a calibration phase, based upon the reference signal. The signal presence detection module may be further configured to receive an input signal. The signal presence detection module may be further configured to perform detection, during a signal amplitude detection phase, of a state of the input signal. According to some embodiments, the circuits (and methods) may include a peak detector of the signal presence detection module shared by the calibration and the detection. In some embodiments of the circuits (and methods), the reference generator may be unpowered during the signal amplitude detection phase. The calibration and the detection may share the peak detector based upon time division multiplexing.Type: GrantFiled: February 21, 2019Date of Patent: January 14, 2020Assignee: Marvell World Trade Ltd.Inventors: Lu Wang, Scott E. Meninger
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Publication number: 20200007305Abstract: A circuit and method enables multiple serializer/deserializer (SerDes) data lanes of a physical layer device (PHY) to operate across a broad range of diversified data rates that are independent from lane to lane. The multiple SerDes data lanes may operate at data rates independent from one another. A single low frequency clock is input to the PHY. A frequency of the single low frequency clock is increased via a common integer-N phase-locked loop (PLL) on the PHY to produce a higher frequency clock. Each of the SerDes data lanes is operated, independently, as a fractional-N PLL that employs the higher frequency clock. Use of the common integer-N PLL enables modulation noise of the fractional-N PLLs to be suppressed by moving the modulation noise to higher frequencies where a level of the modulation noise is filtered, avoiding use of high risk noise cancellation techniques.Type: ApplicationFiled: September 12, 2019Publication date: January 2, 2020Inventor: Scott E. Meninger
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Patent number: 10461917Abstract: A circuit and method enables multiple serializer/deserializer (SerDes) data lanes of a physical layer device (PHY) to operate across a broad range of diversified data rates that are independent from lane to lane. The multiple SerDes data lanes may operate at data rates independent from one another. A single low frequency clock is input to the PHY. A frequency of the single low frequency clock is increased via a common integer-N phase-locked loop (PLL) on the PHY to produce a higher frequency clock. Each of the SerDes data lanes is operated, independently, as a fractional-N PLL that employs the higher frequency clock. Use of the common integer-N PLL enables modulation noise of the fractional-N PLLs to be suppressed by moving the modulation noise to higher frequencies where a level of the modulation noise is filtered, avoiding use of high risk noise cancellation techniques.Type: GrantFiled: March 13, 2019Date of Patent: October 29, 2019Assignee: Cavium, LLCInventor: Scott E. Meninger
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Patent number: 10396803Abstract: A clock and data recovery (CDR) circuit operates to recover a clock and sample data from full-rate and sub-rate data signals. The CDR circuit selectively shifts one or more of the sampling clocks based on the rate of a received data signal, facilitating accurate sampling of sub-rate data signals. A masking circuit selectively masks data output bits clocked by a selection of the sampling clocks, thereby outputting relevant sampled data.Type: GrantFiled: October 19, 2018Date of Patent: August 27, 2019Assignee: Marvell International Ltd.Inventors: Scott E. Meninger, Ethan Crain, Mark Spaeth
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Publication number: 20190215142Abstract: A circuit and method enables multiple serializer/deserializer (SerDes) data lanes of a physical layer device (PHY) to operate across a broad range of diversified data rates that are independent from lane to lane. The multiple SerDes data lanes may operate at data rates independent from one another. A single low frequency clock is input to the PHY. A frequency of the single low frequency clock is increased via a common integer-N phase-locked loop (PLL) on the PHY to produce a higher frequency clock. Each of the SerDes data lanes is operated, independently, as a fractional-N PLL that employs the higher frequency clock. Use of the common integer-N PLL enables modulation noise of the fractional-N PLLs to be suppressed by moving the modulation noise to higher frequencies where a level of the modulation noise is filtered, avoiding use of high risk noise cancellation techniques.Type: ApplicationFiled: March 13, 2019Publication date: July 11, 2019Inventor: Scott E. Meninger
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Publication number: 20190214997Abstract: A clock and data recovery (CDR) circuit operates to recover a clock and sample data from full-rate and sub-rate data signals. The CDR circuit selectively shifts one or more of the sampling clocks based on the rate of a received data signal, facilitating accurate sampling of sub-rate data signals. A masking circuit selectively masks data output bits clocked by a selection of the sampling clocks, thereby outputting relevant sampled data.Type: ApplicationFiled: October 19, 2018Publication date: July 11, 2019Inventors: Scott E. Meninger, Ethan Crain, Mark Spaeth
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Publication number: 20190182022Abstract: In some embodiments, the circuits (and methods) may include a reference generator configured to generate a reference signal. The circuits (and methods) may also include a signal presence detection module configured to perform calibration on itself, during a calibration phase, based upon the reference signal. The signal presence detection module may be further configured to receive an input signal. The signal presence detection module may be further configured to perform detection, during a signal amplitude detection phase, of a state of the input signal. According to some embodiments, the circuits (and methods) may include a peak detector of the signal presence detection module shared by the calibration and the detection. In some embodiments of the circuits (and methods), the reference generator may be unpowered during the signal amplitude detection phase. The calibration and the detection may share the peak detector based upon time division multiplexing.Type: ApplicationFiled: February 21, 2019Publication date: June 13, 2019Inventors: Lu Wang, Scott E. Meninger
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Publication number: 20190165731Abstract: A method and apparatus select an optimal frequency band of a plurality of frequency bands of a multi-band voltage-controlled oscillator (VCO) to achieve a particular output frequency from the multi-band VCO. The optimal frequency band is selected, automatically, based on performing a one-point calibration phase followed by a multi-point calibration phase. The one-point calibration phase produces an initial frequency band selection and the multi-point calibration phase selects the optimal frequency band from a group of frequency bands including the initial frequency band selection, a higher frequency band consecutively higher in frequency relative to the initial frequency band selection, and a lower frequency band consecutively lower in frequency relative to the initial frequency band selection.Type: ApplicationFiled: November 29, 2017Publication date: May 30, 2019Inventors: Omer O. Yildirim, JingDong Deng, Scott E. Meninger
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Patent number: 10291386Abstract: A circuit and method enables multiple serializer/deserializer (SerDes) data lanes of a physical layer device (PHY) to operate across a broad range of diversified data rates that are independent from lane to lane. The multiple SerDes data lanes may operate at data rates independent from one another. A single low frequency clock is input to the PHY. A frequency of the single low frequency clock is increased via a common integer-N phase-locked loop (PLL) on the PHY to produce a higher frequency clock. Each of the SerDes data lanes is operated, independently, as a fractional-N PLL that employs the higher frequency clock. Use of the common integer-N PLL enables modulation noise of the fractional-N PLLs to be suppressed by moving the modulation noise to higher frequencies where a level of the modulation noise is filtered, avoiding use of high risk noise cancellation techniques.Type: GrantFiled: September 29, 2017Date of Patent: May 14, 2019Assignee: Cavium, LLCInventor: Scott E. Meninger
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Patent number: 10263759Abstract: In some embodiments, the circuits (and methods) may include a reference generator configured to generate a reference signal. The circuits (and methods) may also include a signal presence detection module configured to perform calibration on itself, during a calibration phase, based upon the reference signal. The signal presence detection module may be further configured to receive an input signal. The signal presence detection module may be further configured to perform detection, during a signal amplitude detection phase, of a state of the input signal. According to some embodiments, the circuits (and methods) may include a peak detector of the signal presence detection module shared by the calibration and the detection. In some embodiments of the circuits (and methods), the reference generator may be unpowered during the signal amplitude detection phase. The calibration and the detection may share the peak detector based upon time division multiplexing.Type: GrantFiled: April 26, 2017Date of Patent: April 16, 2019Assignee: Cavium, LLCInventors: Lu Wang, Scott E. Meninger
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Publication number: 20190103956Abstract: A circuit and method enables multiple serializer/deserializer (SerDes) data lanes of a physical layer device (PHY) to operate across a broad range of diversified data rates that are independent from lane to lane. The multiple SerDes data lanes may operate at data rates independent from one another. A single low frequency clock is input to the PHY. A frequency of the single low frequency clock is increased via a common integer-N phase-locked loop (PLL) on the PHY to produce a higher frequency clock. Each of the SerDes data lanes is operated, independently, as a fractional-N PLL that employs the higher frequency clock. Use of the common integer-N PLL enables modulation noise of the fractional-N PLLs to be suppressed by moving the modulation noise to higher frequencies where a level of the modulation noise is filtered, avoiding use of high risk noise cancellation techniques.Type: ApplicationFiled: September 29, 2017Publication date: April 4, 2019Inventor: Scott E. Meninger
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Publication number: 20180316526Abstract: In some embodiments, the circuits (and methods) may include a reference generator configured to generate a reference signal. The circuits (and methods) may also include a signal presence detection module configured to perform calibration on itself, during a calibration phase, based upon the reference signal. The signal presence detection module may be further configured to receive an input signal. The signal presence detection module may be further configured to perform detection, during a signal amplitude detection phase, of a state of the input signal. According to some embodiments, the circuits (and methods) may include a peak detector of the signal presence detection module shared by the calibration and the detection. In some embodiments of the circuits (and methods), the reference generator may be unpowered during the signal amplitude detection phase. The calibration and the detection may share the peak detector based upon time division multiplexing.Type: ApplicationFiled: April 26, 2017Publication date: November 1, 2018Inventors: Lu Wang, Scott E. Meninger
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Patent number: 9966964Abstract: An example embodiment disclosed herein enables at least one frequency divider chain of a multiphase divider circuit to ensure proper phase relations after multiple frequency divisions. Another example embodiment enables a unique reset sequence to maximize a timing margin for reset signals of the at least one frequency divider chain and, thus, maximizes a bandwidth of the multiphase divider circuit.Type: GrantFiled: May 23, 2017Date of Patent: May 8, 2018Assignee: Cavium, Inc.Inventors: Scott E. Meninger, JingDong Deng
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Patent number: 9698808Abstract: A circuit provides for phase adjustment of an offset clock pair, and includes an analog stage and a digital stage. The analog stage provides for generating an adjusted offset clock pair and detecting a phase difference between the adjusted offset clock pair. The digital stage operates to quantify the phase difference and provide a command for further adjusting the phase of the adjusted offset clock pair, at the analog stage, towards a target phase offset value.Type: GrantFiled: October 27, 2016Date of Patent: July 4, 2017Assignee: Cavium, Inc.Inventors: Scott E. Meninger, Lu Wang
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Patent number: 9673753Abstract: In an embodiment, a voltage-controlled oscillator circuit includes a gain element and an LC resonator coupled with the gain element, the LC resonator including an inductor section and a capacitor section. The capacitor section has at least two branches connected in parallel and a voltage control input for tuning the LC resonator. Any of the at least two branches is selected from the group of DC-coupled and AC-coupled. Characteristics of the two branches and bias voltages of the AC-coupled branches are selected to provide a tuning curve of the voltage-controlled oscillator circuit that is approximately linear.Type: GrantFiled: January 19, 2016Date of Patent: June 6, 2017Assignee: CAVIUM, INC.Inventors: Omer O. Yildirim, JingDong Deng, Scott E. Meninger
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Patent number: 9496012Abstract: According to at least one example embodiment, a method and corresponding system, or circuit, for calibrating a reference voltage of a single-ended receiver, include applying a clock signal and a reference voltage signal as inputs to the differential amplifier of the single-ended receiver. The differential amplifier provides an output signal, the output signal is processed, and an indication of a duty cycle associated with an output signal of the amplifier is evaluated. Based on the evaluated indication of the duty cycle, a control logic module, or circuit, adjusts a level of the reference voltage signal. The process of evaluating the indication of the duty cycle and adjusting the reference voltage level is repeated for a number of iterations.Type: GrantFiled: September 27, 2013Date of Patent: November 15, 2016Assignee: Cavium, Inc.Inventors: Omer O. Yildirim, David Lin, Scott E. Meninger