Abstract: An apparatus includes a plurality of semiconductor devices and an electrical input device for applying voltage to the plurality of semiconductor devices. There is a switching array configured to sequentially interconnect the electrical input device to each of the semiconductor devices and disconnect the other semiconductor devices from the electrical input device. The semiconductor device connected to the electrical input device is a device under test that produces a test current and the other semiconductor devices are devices not under test that produce, in the aggregate, a leakage current. There is an output node interconnected to the switching array for enabling the measurement of the test current at the output node. There is also a leakage current compensator connected to the output node and the switching array that is configured to divert the leakage current away from the output node.

Abstract: According to at least one example embodiment a two phase calibration approach is employed for calibrating an input/output interface having multiple single-ended receivers. During a first phase, amplifier offset calibration is applied to each of the multiple single-ended receivers. During a second phase, reference voltage calibration is applied to a single-ended receiver of the multiple single-ended receivers to determine a calibration reference voltage value. The calibration reference voltage value is then employed in each of the multiple single-ended receivers during an active phase of the input/output interface.

Abstract: An apparatus includes a plurality of semiconductor devices and an electrical input device for applying voltage to the plurality of semiconductor devices. There is a switching array configured to sequentially interconnect the electrical input device to each of the semiconductor devices and disconnect the other semiconductor devices from the electrical input device. The semiconductor device connected to the electrical input device is a device under test that produces a test current and the other semiconductor devices are devices not under test that produce, in the aggregate, a leakage current. There is an output node interconnected to the switching array for enabling the measurement of the test current at the output node. There is also a leakage current compensator connected to the output node and the switching array that is configured to divert the leakage current away from the output node.

Abstract: According to at least one example embodiment, a method and corresponding system for calibrating an amplifier offset include applying an input value to both input leads of an amplifier. The amplifier includes one or more digital-to-analog converters (DACs) used to calibrate an offset of the amplifier. A digital value, provided as input to the DAC, is updated over a number of iterations, by a control logic coupled to the amplifier, based on an output of the amplifier. A final value of the digital value being updated, e.g., associated with the last iteration, is employed as input to the DAC of the one or more DACs in the amplifier for calibrating the offset of the amplifier during a data reception phase.

Abstract: According to at least one example embodiment, a method and corresponding system, or circuit, for calibrating a reference voltage of a single-ended receiver, include applying a clock signal and a reference voltage signal as inputs to the differential amplifier of the single-ended receiver. The differential amplifier provides an output signal, the output signal is processed, and an indication of a duty cycle associated with an output signal of the amplifier is evaluated. Based on the evaluated indication of the duty cycle, a control logic module, or circuit, adjusts a level of the reference voltage signal. The process of evaluating the indication of the duty cycle and adjusting the reference voltage level is repeated for a number of iterations.

Abstract: According to at least one example embodiment, a method and corresponding system for calibrating an amplifier offset include applying an input value to both input leads of an amplifier. The amplifier includes one or more digital-to-analog converters (DACs) used to calibrate an offset of the amplifier. A digital value, provided as input to the DAC, is updated over a number of iterations, by a control logic coupled to the amplifier, based on an output of the amplifier. A final value of the digital value being updated, e.g., associated with the last iteration, is employed as input to the DAC of the one or more DACs in the amplifier for calibrating the offset of the amplifier during a data reception phase.

Abstract: According to at least one example embodiment a two phase calibration approach is employed for calibrating an input/output interface having multiple single-ended receivers. During a first phase, amplifier offset calibration is applied to each of the multiple single-ended receivers. During a second phase, reference voltage calibration is applied to a single-ended receiver of the multiple single-ended receivers to determine a calibration reference voltage value. The calibration reference voltage value is then employed in each of the multiple single-ended receivers during an active phase of the input/output interface.