Patents by Inventor Scott E. Sills

Scott E. Sills has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230014320
    Abstract: An array of vertical transistors comprises spaced pillars of individual vertical transistors that individually comprise an upper source/drain region, a lower source/drain region, and a channel region vertically there-between. The upper source/drain region comprises a conductor oxide material in individual of the pillars. The channel region comprises an oxide semiconductor material in the individual pillars. The lower source/drain region comprises a first conductive oxide material in the individual pillars atop and directly against a second conductive oxide material in the individual pillars. Horizontally-elongated and spaced conductor lines individually interconnect a respective multiple of the vertical transistors in a column direction. The conductor lines individually comprise the second conductive oxide material atop and directly against metal material. The first conductive oxide material, the second conductive oxide material, and the metal material comprise different compositions relative one another.
    Type: Application
    Filed: September 19, 2022
    Publication date: January 19, 2023
    Applicant: Micron Technology, Inc.
    Inventors: Yi Fang Lee, Jaydip Guha, Lars P. Heineck, Kamal M. Karda, Si-Woo Lee, Terrence B. McDaniel, Scott E. Sills, Kevin J. Torek, Sheng-Wei Yang
  • Publication number: 20220416088
    Abstract: A method of forming a device comprises forming dielectric structures over other dielectric structures overlying conductive contact structures, the dielectric structures separated from one another by trenches and laterally extending orthogonal to the other dielectric structures and the conductive contact structures. Conductive gate structures are formed on exposed side surfaces of the dielectric structures within the trenches. Dielectric oxide structures are formed on exposed side surfaces of the conductive gate structures within the trenches. Exposed portions of the other dielectric structures are removed to form isolation structures. Semiconductive pillars are formed on exposed side surfaces of the dielectric oxide structures and the isolation structures within the trenches. The semiconductive pillars are in electrical contact with the conductive contact structures. Additional conductive contact structures are formed on upper surfaces of the semiconductive pillars.
    Type: Application
    Filed: August 25, 2022
    Publication date: December 29, 2022
    Inventors: Scott E. Sills, Ramanathan Gandhi, Durai Vishak Nirmal Ramaswamy
  • Publication number: 20220406899
    Abstract: Some embodiments include an integrated assembly containing a first structure which includes one or more transition metals, and containing a second structure over the first structure. The second structure has a first region directly against the first structure and has a second region spaced from the first structure by a gap region. The second structure includes semiconductor material having at least one element selected from Group 13 of the periodic table in combination with at least one element selected from Groups 15 and 16 of the periodic table. An ionic compound is within the gap region. Some embodiments include a method of forming an integrated assembly.
    Type: Application
    Filed: June 17, 2021
    Publication date: December 22, 2022
    Applicant: Micron Technology, Inc.
    Inventors: Yoshitaka Nakamura, Devesh Dadhich Shreeram, Yi Fang Lee, Scott E. Sills, Jerome A. Imonigie, Kaustubh Shrimali
  • Patent number: 11527620
    Abstract: Some embodiments include an integrated assembly having a polycrystalline first semiconductor material, and having a second semiconductor material directly adjacent to the polycrystalline first semiconductor material. The second semiconductor material is of a different composition than the polycrystalline first semiconductor material. A conductivity-enhancing dopant is within the second semiconductor material. The conductivity-enhancing dopant is a neutral-type dopant relative to the polycrystalline first semiconductor material. An electrical gate is adjacent to a region of the polycrystalline first semiconductor material and is configured to induce an electric field within said region of the polycrystalline first semiconductor material. The gate is not adjacent to the second semiconductor material.
    Type: Grant
    Filed: May 11, 2021
    Date of Patent: December 13, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Kamal M. Karda, Deepak Chandra Pandey, Haitao Liu, Richard J. Hill, Guangyu Huang, Yunfei Gao, Ramanathan Gandhi, Scott E. Sills
  • Patent number: 11515417
    Abstract: A transistor comprises a first conductive contact, a heterogeneous channel comprising at least one oxide semiconductor material over the first conductive contact, a second conductive contact over the heterogeneous channel, and a gate electrode laterally neighboring the heterogeneous channel. A device, a method of forming a device, a memory device, and an electronic system are also described.
    Type: Grant
    Filed: October 8, 2019
    Date of Patent: November 29, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Scott E. Sills, Ramanathan Gandhi, Durai Vishak Nirmal Ramaswamy, Yi Fang Lee, Kamal M. Karda
  • Patent number: 11488981
    Abstract: An array of vertical transistors comprises spaced pillars of individual vertical transistors that individually comprise an upper source/drain region, a lower source/drain region, and a channel region vertically there-between. The upper source/drain region comprises a conductor oxide material in individual of the pillars. The channel region comprises an oxide semiconductor material in the individual pillars. The lower source/drain region comprises a first conductive oxide material in the individual pillars atop and directly against a second conductive oxide material in the individual pillars. Horizontally-elongated and spaced conductor lines individually interconnect a respective multiple of the vertical transistors in a column direction. The conductor lines individually comprise the second conductive oxide material atop and directly against metal material. The first conductive oxide material, the second conductive oxide material, and the metal material comprise different compositions relative one another.
    Type: Grant
    Filed: July 21, 2020
    Date of Patent: November 1, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Yi Fang Lee, Jaydip Guha, Lars P. Heineck, Kamal M. Karda, Si-Woo Lee, Terrence B. McDaniel, Scott E. Sills, Kevin J. Torek, Sheng-Wei Yang
  • Patent number: 11476251
    Abstract: Systems, methods and apparatus are provided for a three-node access device in vertical three dimensional (3D) memory. An example method includes a method for forming arrays of vertically stacked memory cells, having horizontally oriented access devices and vertically oriented access lines. The method includes depositing alternating layers of a dielectric material and a sacrificial material in repeating iterations to form a vertical stack. An etchant process is used to form a first vertical opening exposing vertical sidewalls in the vertical stack adjacent a first region. The first region is selectively etched to form a first horizontal opening removing the sacrificial material a first horizontal distance back from the first vertical opening.
    Type: Grant
    Filed: August 6, 2020
    Date of Patent: October 18, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Scott E. Sills, John A. Smythe, III, Si-Woo Lee, Gurtej S. Sandhu, Armin Saeedi Vahdat
  • Patent number: 11476259
    Abstract: A device comprises a vertical transistor. The vertical transistor comprises a semiconductive pillar, at least one gate electrode, a gate dielectric material, and void spaces. The semiconductive pillar comprises a source region, a drain region, and a channel region extending vertically between the source region and the drain region, the channel region comprising a semiconductive material having a band gap greater than 1.65 electronvolts. The at least one gate electrode laterally neighbors the semiconductive pillar. The gate dielectric material is laterally between the semiconductive pillar and the at least one gate electrode. The void spaces are vertically adjacent the gate dielectric material and laterally intervening between the at least one gate electrode and each of the source region and the drain region of the semiconductive pillar. Related electronic systems and methods are also disclosed.
    Type: Grant
    Filed: April 14, 2021
    Date of Patent: October 18, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Kamal M. Karda, Ramanathan Gandhi, Hong Li, Haitao Liu, Durai Vishak Nirmal Ramaswamy, Sanh D. Tang, Scott E. Sills
  • Publication number: 20220310637
    Abstract: Some embodiments include an integrated transistor having an active region comprising semiconductor material. A conductive gating structure is adjacent to the active region. The conductive gating structure includes an inner region proximate the active region and includes an outer region distal from the active region. The inner region includes a first material containing titanium and nitrogen, and the outer region includes a metal-containing second material. The second material has a higher conductivity than the first material. Some embodiments include integrated assemblies. Some embodiments include methods of forming integrated assemblies.
    Type: Application
    Filed: March 29, 2021
    Publication date: September 29, 2022
    Applicant: Micron Technology, Inc.
    Inventors: Aaron Michael Lowe, Zhuo Chen, Marko Milojevic, Timothy A. Quick, Richard J. Hill, Scott E. Sills
  • Publication number: 20220310831
    Abstract: Some embodiments include an integrated assembly having a conductive structure, an annular structure extending through the conductive structure, and an active-material-structure lining an interior periphery of the annular structure. The annular structure includes dielectric material. The active-material-structure includes two-dimensional-material. Some embodiments include methods of forming integrated assemblies.
    Type: Application
    Filed: June 14, 2022
    Publication date: September 29, 2022
    Applicant: Micron Technology, Inc.
    Inventors: David K. Hwang, John F. Kaeding, Richard J. Hill, Scott E. Sills
  • Publication number: 20220302317
    Abstract: A device comprises a vertical transistor. The vertical transistor comprises a semiconductive pillar, at least one gate electrode, a gate dielectric material, and void spaces. The semiconductive pillar comprises a source region, a drain region, and a channel region extending vertically between the source region and the drain region, the channel region comprising a semiconductive material having a band gap greater than 1.65 electronvolts. The at least one gate electrode laterally neighbors the semiconductive pillar. The gate dielectric material is laterally between the semiconductive pillar and the at least one gate electrode. The void spaces are vertically adjacent the gate dielectric material and laterally intervening between the at least one gate electrode and each of the source region and the drain region of the semiconductive pillar. Related electronic systems and methods are also disclosed.
    Type: Application
    Filed: April 14, 2021
    Publication date: September 22, 2022
    Inventors: Kamal M. Karda, Ramanathan Gandhi, Hong Li, Haitao Liu, Durai Vishak Nirmal Ramaswamy, Sanh D. Tang, Scott E. Sills
  • Publication number: 20220302318
    Abstract: A device comprises vertically oriented transistors. The device comprises a pillar comprising at least one oxide semiconductor material, the pillar wider in a first lateral direction at an upper portion thereof than at a lower portion thereof, a gate dielectric material over sidewalls of the pillar and extending in the first lateral direction, and at least one gate electrode adjacent to at least a portion of the gate dielectric material. Related devices, electronic systems, and methods are also disclosed.
    Type: Application
    Filed: June 10, 2022
    Publication date: September 22, 2022
    Inventors: Durai Vishak Nirmal Ramaswamy, Scott E. Sills
  • Patent number: 11437521
    Abstract: A method of forming a device comprises forming dielectric structures over other dielectric structures overlying conductive contact structures, the dielectric structures separated from one another by trenches and laterally extending orthogonal to the other dielectric structures and the conductive contact structures. Conductive gate structures are formed on exposed side surfaces of the dielectric structures within the trenches. Dielectric oxide structures are formed on exposed side surfaces of the conductive gate structures within the trenches. Exposed portions of the other dielectric structures are removed to form isolation structures. Semiconductive pillars are formed on exposed side surfaces of the dielectric oxide structures and the isolation structures within the trenches. The semiconductive pillars are in electrical contact with the conductive contact structures. Additional conductive contact structures are formed on upper surfaces of the semiconductive pillars.
    Type: Grant
    Filed: October 8, 2019
    Date of Patent: September 6, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Scott E. Sills, Ramanathan Gandhi, Durai Vishak Nirmal Ramaswamy
  • Patent number: 11424241
    Abstract: A semiconductor device comprises a stack structure comprising decks each comprising a memory element level comprising memory elements, and a control logic level in electrical communication with the memory element level and comprising control logic devices. At least one of the control logic devices of the control logic level of one or more of the decks comprises at least one device exhibiting transistors laterally displaced from one another. A memory device, a thin film transistor control logic assembly, an electronic system, and a method of operating a semiconductor device are also described.
    Type: Grant
    Filed: June 16, 2020
    Date of Patent: August 23, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Scott E. Sills, Kurt D. Beigel
  • Publication number: 20220252245
    Abstract: A solid state lighting (SSL) with a solid state emitter (SSE) having thermally conductive projections extending into an air channel, and methods of making and using such SSLs. The thermally conductive projections can be fins, posts, or other structures configured to transfer heat into a fluid medium, such as air. The projections can be electrical contacts between the SSE and a power source. The air channel can be oriented generally vertically such that air in the channel warmed by the SSE flows upward through the channel.
    Type: Application
    Filed: April 25, 2022
    Publication date: August 11, 2022
    Inventor: Scott E. Sills
  • Publication number: 20220254896
    Abstract: A semiconductor device is disclosed. The semiconductor device includes a transistor including a source contact, a drain contact, and a channel region including an oxide semiconductor material as the channel material. At least one of the drain contact or the source contact includes a conductive material, such as ruthenium, to reduce the Schottky effects at the interface with the channel material.
    Type: Application
    Filed: April 28, 2022
    Publication date: August 11, 2022
    Inventors: Durai Vishak Nirmal Ramaswamy, Ramanathan Gandhi, Scott E. Sills
  • Publication number: 20220238658
    Abstract: Some embodiments include an integrated assembly having a gate material, an insulative material adjacent the gate material, and a semiconductor oxide adjacent the insulative material. The semiconductor oxide has a channel region proximate the gate material and spaced from the gate material by the insulative material. An electric field along the gate material induces carrier flow within the channel region, with the carrier flow being along a first direction. The semiconductor oxide includes a grain boundary having a portion which extends along a second direction that crosses the first direction of the carrier flow. In some embodiments, the semiconductor oxide has a grain boundary which extends along the first direction and which is offset from the insulative material by an intervening portion of the semiconductor oxide. The carrier flow is within the intervening region and substantially parallel to the grain boundary. Some embodiments include methods of forming integrated assemblies.
    Type: Application
    Filed: April 13, 2022
    Publication date: July 28, 2022
    Applicant: Micron Technology, Inc.
    Inventors: Yi Fang Lee, Isamu Asano, Ramanathan Gandhi, Scott E. Sills
  • Patent number: 11398571
    Abstract: A device comprises vertically oriented transistors. The device comprises a pillar comprising at least one oxide semiconductor material, the pillar wider in a first lateral direction at an upper portion thereof than at a lower portion thereof, a gate dielectric material over sidewalls of the pillar and extending in the first lateral direction, and at least one gate electrode adjacent to at least a portion of the gate dielectric material. Related devices, electronic systems, and methods are also disclosed.
    Type: Grant
    Filed: October 8, 2019
    Date of Patent: July 26, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Durai Vishak Nirmal Ramaswamy, Scott E. Sills
  • Patent number: 11393978
    Abstract: An array of cross point memory cells comprises spaced first lines which cross spaced second lines. Two memory cells are individually between one of two immediately adjacent of the second lines and a same single one of the first lines.
    Type: Grant
    Filed: July 16, 2020
    Date of Patent: July 19, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Scott E. Sills, Durai Vishak Nirmal Ramaswamy, Alessandro Calderoni
  • Patent number: 11393920
    Abstract: Some embodiments include an integrated assembly having a conductive structure, an annular structure extending through the conductive structure, and an active-material-structure lining an interior periphery of the annular structure. The annular structure includes dielectric material. The active-material-structure includes two-dimensional-material. Some embodiments include methods of forming integrated assemblies.
    Type: Grant
    Filed: September 28, 2020
    Date of Patent: July 19, 2022
    Assignee: Micron Technology, Inc.
    Inventors: David K. Hwang, John F. Kaeding, Richard J. Hill, Scott E. Sills