Patents by Inventor Scott E. Sills

Scott E. Sills has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200013955
    Abstract: A resistive memory element comprises a first electrode, an active material over the first electrode, a buffer material over the active material and comprising longitudinally extending, columnar grains of crystalline material, an ion reservoir material over the buffer material, and a second electrode over the ion reservoir material. A memory cell, a memory device, an electronic system, and a method of forming a resistive memory element are also described.
    Type: Application
    Filed: August 27, 2019
    Publication date: January 9, 2020
    Inventors: Christopher W. Petz, Yongjun Jeff Hu, Scott E. Sills, D. V. Nirmal Ramaswamy
  • Patent number: 10529720
    Abstract: A method of forming an array of capacitors and access transistors there-above comprises forming access transistor trenches partially into insulative material. The trenches individually comprise longitudinally-spaced masked portions and longitudinally-spaced openings in the trenches longitudinally between the masked portions. The trench openings have walls therein extending longitudinally in and along the individual trench openings against laterally-opposing sides of the trenches. At least some of the insulative material that is under the trench openings is removed through bases of the trench openings between the walls and the masked portions to form individual capacitor openings in the insulative material that is lower than the walls. Individual capacitors are formed in the individual capacitor openings. A line of access transistors is formed in the individual trenches. The line of access transistors electrically couples to the individual capacitors that are along that line.
    Type: Grant
    Filed: January 3, 2019
    Date of Patent: January 7, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Scott E. Sills, Durai Vishak Nirmal Ramaswamy
  • Publication number: 20190386063
    Abstract: A method of forming an array of memory cells includes forming lines of covering material that are elevationally over and along lines of spaced sense line contacts. Longitudinal orientation of the lines of covering material is used in forming lines comprising programmable material and outer electrode material that are between and along the lines of covering material. The covering material is removed over the spaced sense line contacts and the spaced sense line contacts are exposed. Access lines are formed. Sense lines are formed that are electrically coupled to the spaced sense line contacts. The sense lines are angled relative to the lines of spaced sense line contacts and relative to the access lines. Other embodiments, including structure independent of method, are disclosed.
    Type: Application
    Filed: August 30, 2019
    Publication date: December 19, 2019
    Applicant: Micron Technology, Inc.
    Inventors: Scott E. Sills, Durai Vishak Nirmal Ramaswamy
  • Publication number: 20190363253
    Abstract: Methods of forming conductive elements, such as interconnects and electrodes, for semiconductor structures and memory cells. The methods include forming a first conductive material and a second conductive material comprising silver in a portion of at least one opening and performing a polishing process to fill the at least one opening with at least one of the first and second conductive materials. An annealing process may be performed to form a mixture or an alloy of the silver and the first conductive material. The methods enable formation of silver-containing conductive elements having reduced dimensions (e.g., less than about 20 nm). The resulting conductive elements have a desirable resistivity. The methods may be used, for example, to form interconnects for electrically connecting active devices and to form electrodes for memory cells. A semiconductor structure and a memory cell including such a conductive structure are also disclosed.
    Type: Application
    Filed: August 12, 2019
    Publication date: November 28, 2019
    Inventors: Sanh D. Tang, Scott E. Sills, Whitney L. West, Rob B. Goodwin, Nishant Sinha
  • Patent number: 10490740
    Abstract: A method of manufacture of a non-volatile memory system comprising: forming a dielectric layer having a hole; depositing a first electrode in the hole of the dielectric layer; applying an ion source layer over the first electrode; and depositing a second electrode over the ion source layer including: depositing an interface layer on the ion source layer, and applying a cap layer on the interface layer.
    Type: Grant
    Filed: August 9, 2013
    Date of Patent: November 26, 2019
    Assignee: Sony Semiconductor Solutions Corporation
    Inventors: Shuichiro Yasuda, Dale Collins, Scott E. Sills
  • Publication number: 20190348413
    Abstract: A semiconductor device includes a stack structure comprising decks. Each deck of the stack structure comprises a memory element level comprising memory elements and control logic level in electrical communication with the memory element level, the control logic level comprising a first subdeck structure comprising a first number of transistors comprising a P-type channel region or an N-type channel region and a second subdeck structure comprising a second number of transistors comprising the other of the P-type channel region or the N-type channel region overlying the first subdeck structure. Related semiconductor devices and methods of forming the semiconductor devices are disclosed.
    Type: Application
    Filed: July 24, 2019
    Publication date: November 14, 2019
    Inventors: Kurt D. Beigel, Scott E. Sills
  • Patent number: 10446751
    Abstract: A resistive memory element comprises a first electrode, an active material over the first electrode, a buffer material over the active material and comprising longitudinally extending, columnar grains of crystalline material, an ion reservoir material over the buffer material, and a second electrode over the ion reservoir material. A memory cell, a memory device, an electronic system, and a method of forming a resistive memory element are also described.
    Type: Grant
    Filed: January 17, 2018
    Date of Patent: October 15, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Christopher W. Petz, Yongjun Jeff Hu, Scott E. Sills, D. V. Nirmal Ramaswamy
  • Publication number: 20190304970
    Abstract: A semiconductor device comprises a stack structure comprising decks each comprising a memory element level comprising memory elements, and a control logic level in electrical communication with the memory element level and comprising control logic devices. At least one of the control logic devices of the control logic level of one or more of the decks comprises at least one device exhibiting transistors laterally displaced from one another. A memory device, a thin film transistor control logic assembly, an electronic system, and a method of operating a semiconductor device are also described.
    Type: Application
    Filed: June 17, 2019
    Publication date: October 3, 2019
    Inventors: Scott E. Sills, Kurt D. Beigel
  • Patent number: 10431629
    Abstract: A method of forming an array of memory cells includes forming lines of covering material that are elevationally over and along lines of spaced sense line contacts. Longitudinal orientation of the lines of covering material is used in forming lines comprising programmable material and outer electrode material that are between and along the lines of covering material. The covering material is removed over the spaced sense line contacts and the spaced sense line contacts are exposed. Access lines are formed. Sense lines are formed that are electrically coupled to the spaced sense line contacts. The sense lines are angled relative to the lines of spaced sense line contacts and relative to the access lines. Other embodiments, including structure independent of method, are disclosed.
    Type: Grant
    Filed: May 23, 2018
    Date of Patent: October 1, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Scott E. Sills, Durai Vishak Nirmal Ramaswamy
  • Publication number: 20190296235
    Abstract: Some embodiments include a method of forming a memory cell. A first portion of a switching region is formed over a first electrode. A second portion of the switching region is formed over the first portion using atomic layer deposition. The second portion is a different composition than the first portion. An ion source region is formed over the switching region. A second electrode is formed over the ion source region. Some embodiments include a memory cell having a switching region between a pair of electrodes. The switching region is configured to be reversibly transitioned between a low resistive state and a high resistive state. The switching region includes two or more discrete portions, with one of the portions not having a non-oxygen component in common with any composition directly against it in the high resistive state.
    Type: Application
    Filed: June 13, 2019
    Publication date: September 26, 2019
    Applicant: Micron Technology, Inc.
    Inventors: Shuichiro Yasuda, Noel Rocklein, Scott E. Sills, Durai Vishal Nirmal Ramaswamy, Qian Tao
  • Publication number: 20190296023
    Abstract: A memory cell comprises first and second transistors laterally displaced relative one another. A capacitor is above the first and second transistors. The capacitor comprises a container-shape conductive first capacitor node electrically coupled with a first current node of the first transistor, a conductive second capacitor node electrically coupled with a first current node of the second transistor, and a capacitor dielectric material between the first capacitor node and the second capacitor node. The capacitor dielectric material extends across a top of the container-shape first capacitor node. Additional embodiments and aspects, including method, are disclosed.
    Type: Application
    Filed: June 14, 2019
    Publication date: September 26, 2019
    Applicant: Micron Technology, Inc.
    Inventor: Scott E. Sills
  • Patent number: 10424481
    Abstract: A method of forming a semiconductor device structure comprises forming a preliminary structure comprising a substrate, a photoresist material over the substrate, and a plurality of structures longitudinally extending through the photoresist material and at least partially into the substrate. The preliminary structure is exposed to electromagnetic radiation directed toward upper surfaces of the photoresist material and the plurality of structures at an angle non-orthogonal to the upper surfaces to form a patterned photoresist material. The patterned photoresist material is developed to selectively remove some regions of the patterned photoresist material relative to other regions of the patterned photoresist material. Linear structures substantially laterally aligned with at least some structures of the plurality of structures are formed using the other regions of the patterned photoresist material. Additional methods of forming a semiconductor device structure are also described.
    Type: Grant
    Filed: November 2, 2018
    Date of Patent: September 24, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Scott E. Sills, Gurtej S. Sandhu
  • Patent number: 10410925
    Abstract: Some embodiments include an assembly having a CMOS tier. The CMOS tier includes a PMOS deck and an NMOS deck, with the decks being vertically offset relative to one another. The PMOS deck has p-channel transistors which are substantially identical to one another, and the NMOS deck has n-channel transistors which are substantially identical to one another. An insulative region is between the PMOS deck and the NMOS deck. The CMOS tier has one or more circuit components which include one or more of the n-channel transistors coupled with one or more of the p-channel transistors through one or more conductive interconnects extending through the insulative region. Some embodiments include methods of forming assemblies to comprise one or more CMOS tiers.
    Type: Grant
    Filed: December 29, 2017
    Date of Patent: September 10, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Scott E. Sills, Kurt D. Beigel
  • Patent number: 10408443
    Abstract: A solid state lighting (SSL) with a solid state emitter (SSE) having thermally conductive projections extending into an air channel, and methods of making and using such SSLs. The thermally conductive projections can be fins, posts, or other structures configured to transfer heat into a fluid medium, such as air. The projections can be electrical contacts between the SSE and a power source. The air channel can be oriented generally vertically such that air in the channel warmed by the SSE flows upward through the channel.
    Type: Grant
    Filed: October 9, 2017
    Date of Patent: September 10, 2019
    Assignee: Micron Technology, Inc.
    Inventor: Scott E. Sills
  • Patent number: 10411186
    Abstract: Methods of forming conductive elements, such as interconnects and electrodes, for semiconductor structures and memory cells. The methods include forming a first conductive material and a second conductive material comprising silver in a portion of at least one opening and performing a polishing process to fill the at least one opening with at least one of the first and second conductive materials. An annealing process may be performed to form a mixture or an alloy of the silver and the first conductive material. The methods enable formation of silver-containing conductive elements having reduced dimensions (e.g., less than about 20 nm). The resulting conductive elements have a desirable resistivity. The methods may be used, for example, to form interconnects for electrically connecting active devices and to form electrodes for memory cells. A semiconductor structure and a memory cell including such a conductive structure are also disclosed.
    Type: Grant
    Filed: December 20, 2017
    Date of Patent: September 10, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Sanh D. Tang, Scott E. Sills, Whitney L. West, Rob B. Goodwin, Nishant Sinha
  • Publication number: 20190271459
    Abstract: A solid state lighting (SSL) with a solid state emitter (SSE) having thermally conductive projections extending into an air channel, and methods of making and using such SSLs. The thermally conductive projections can be fins, posts, or other structures configured to transfer heat into a fluid medium, such as air. The projections can be electrical contacts between the SSE and a power source. The air channel can be oriented generally vertically such that air in the channel warmed by the SSE flows upward through the channel.
    Type: Application
    Filed: May 19, 2019
    Publication date: September 5, 2019
    Inventor: Scott E. Sills
  • Publication number: 20190259663
    Abstract: Some embodiments include an assembly having a CMOS tier. The CMOS tier includes a PMOS deck and an NMOS deck, with the decks being vertically offset relative to one another. The PMOS deck has p-channel transistors which are substantially identical to one another, and the NMOS deck has n-channel transistors which are substantially identical to one another. An insulative region is between the PMOS deck and the NMOS deck. The CMOS tier has one or more circuit components which include one or more of the n-channel transistors coupled with one or more of the p-channel transistors through one or more conductive interconnects extending through the insulative region. Some embodiments include methods of forming assemblies to comprise one or more CMOS tiers.
    Type: Application
    Filed: May 3, 2019
    Publication date: August 22, 2019
    Applicant: Micron Technology, Inc.
    Inventors: Scott E. Sills, Kurt D. Beigel
  • Patent number: 10388871
    Abstract: Some embodiments include a method of forming a memory cell. A first portion of a switching region is formed over a first electrode. A second portion of the switching region is formed over the first portion using atomic layer deposition. The second portion is a different composition than the first portion. An ion source region is formed over the switching region. A second electrode is formed over the ion source region. Some embodiments include a memory cell having a switching region between a pair of electrodes. The switching region is configured to be reversibly transitioned between a low resistive state and a high resistive state. The switching region includes two or more discrete portions, with one of the portions not having a non-oxygen component in common with any composition directly against it in the high resistive state.
    Type: Grant
    Filed: October 25, 2016
    Date of Patent: August 20, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Shuichiro Yasuda, Noel Rocklein, Scott E. Sills, Durai Vishak Nirmal Ramaswamy, Qian Tao
  • Patent number: 10366983
    Abstract: A semiconductor device includes a stack structure comprising decks. Each deck of the stack structure comprises a memory element level comprising memory elements and control logic level in electrical communication with the memory element level, the control logic level comprising a first subdeck structure comprising a first number of transistors comprising a P-type channel region or an N-type channel region and a second subdeck structure comprising a second number of transistors comprising the other of the P-type channel region or the N-type channel region overlying the first subdeck structure. Related semiconductor devices and methods of forming the semiconductor devices are disclosed.
    Type: Grant
    Filed: December 29, 2017
    Date of Patent: July 30, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Kurt D. Beigel, Scott E. Sills
  • Patent number: 10355002
    Abstract: A memory cell comprises first and second transistors laterally displaced relative one another. A capacitor is above the first and second transistors. The capacitor comprises a container-shape conductive first capacitor node electrically coupled with a first current node of the first transistor, a conductive second capacitor node electrically coupled with a first current node of the second transistor, and a capacitor dielectric material between the first capacitor node and the second capacitor node. The capacitor dielectric material extends across a top of the container-shape first capacitor node. Additional embodiments and aspects, including method, are disclosed.
    Type: Grant
    Filed: August 2, 2017
    Date of Patent: July 16, 2019
    Assignee: Micron Technology, Inc.
    Inventor: Scott E. Sills