Abstract: A method and apparatus are provided for implementing error injection for peripheral component interconnect (PCI) bridges. The apparatus for implementing error injection for peripheral component interconnect (PCI) bridges includes a plurality of PCI busses and a control logic coupled to the plurality of PCI busses. The control logic targets a selected bus of the plurality of PCI busses. A hit is detected on the selected bus. Responsive to the detected hit, an error is injected on the selected bus. For a detected hit for predefined bug types, the operation must match a selected read or write, target or master, command type and the address must match unmasked address bits. For a detected hit for another predefined bug type, the PCI data bus must also match an unmask data register.

Abstract: An Internet Protocol (IP) telephony system manages Gatekeeper subscriber load by assigning subscriber load among a plurality of Gatekeepers during the Gatekeeper discovery and registration process. A Registration Load Management Unit (RLMU) is primarily responsible for assigning subscriber load to the plurality of Gatekeepers. In one embodiment, the plurality of Gatekeepers are organized without a hierarchy structure and are made up of a plurality of Gatekeeper service nodes and a plurality of Gatekeeper Database nodes. The Gatekeeper service nodes provide the Registration, Admission, Status, Location, Call Set Up and other operating functions of the Gatekeeper while the plurality of Gatekeeper Database nodes store subscriber information. In a second embodiment, the plurality of Gatekeepers are organized in a hierarchy with a Root Gatekeeper at the top of the hierarchy and a plurality of Gatekeepers residing below the Root Gatekeeper in the hierarchy.

Abstract: An apparatus and method for an advanced tunneling technique to allow Internet Protocol (IP) frames to be routed through System Area Network (SAN) components with little or no overhead are provided. Furthermore, an apparatus and method for processing Internet Protocol (IP) version 6 datagrams over a SAN using basic raw and unreliable datagram (RawD and UD respectively) interfaces are provided. The apparatus and method allows a host channel adapter (HCA) to attach directly to an IP router which supports multiple link protocols, for example a router than attaches InfiniBand (IB) links and Ethernet links, and uses IP as the networking protocol on both. In this way, a SAN may be coupled to a LAN via a router with minimal hardware and overhead.

Abstract: An apparatus and method for recording segment execution times in a processing system are provided. The method includes the steps of recording a timestamp corresponding to the beginning of a segment to be executed, wherein the recording step is conducted through a firmware operation. The method further includes the step of updating the timestamp with an elapsed segment execution time, wherein the updating step is conducted through a plurality of hardware based operations that are executed without firmware interaction.

Abstract: A data structure for processing a neural network, and a method of processing a neural network are disclosed. The data structure, which is in a memory device, includes a first data structure portion and a second data structure portion within the memory device. The first data structure portion includes a first plurality of sequential memory locations. Each of the first plurality of sequential memory locations stores a respective input data signal value to be provided to respective inputs of both a first neuron and a second neuron of a first layer of the neural network. The second data structure portion includes a second plurality of sequential memory locations. Each of the second plurality of sequential memory locations stores a respective weight value corresponding to a respective input of a respective one of the first neuron and the second neuron.

Abstract: Applicants provide methods of inhibiting viral infections, and treating an infected individual with AIDS, respiratory syncytial virus infection, parainfluenza virus infection, and other viral infections. Inhibitors of Rho isoprenylation are used to inhibit Rho cell surface attachment, thereby inhibiting the use, by viruses, of Rho as a receptor for infection of susceptible cells. Isoprenylation inhibitors include inhibitors specific for the enzymes farnesyltransferase and geranylgeranyltranferase, as well as inhibitors of general cholesterol biosynthesis, such as HMG-CoA reductase inhibitors.

Abstract: A fusion implant apparatus for facilitating fusion of bone structures includes an implant member for positioning between opposed bone structures having a first ring-like segment and a second ring-like segment which engage one another in an end-to-end manner. Each ring-like segment includes an outer wall which defines an internal cavity for the reception of bone growth inducing substances. Each ring-like segment also includes a plurality of apertures which extend through the outer wall of the ring-like segments in communication with the internal cavity to permit fusion of vertebral bone tissue. The first ring-like segment includes first and second mechanical interfaces. The first mechanical interface is dimensioned to engage a corresponding mechanical interface disposed on the second ring-like segment and the second mechanical interface is dimensioned to mechanically engage an end cap.

Abstract: The present invention is directed toward a framework for consistent and minimized development of Web-based applications. A preferred Web-based application of the present invention is built on a web server framework utilizing industry standard technologies relating to Web development and deployment. These technologies fall into three main areas: browser technology, Web server technology, and application server technology. A preferred Web architecture of the present invention is preferably based on HTTP, utilizing a browser, Middleware, and a Web Server, the Web Server comprising Java servlets, Java Server Pages, Java Beans, and a Web Server Framework. This architecture follows a standard Model, View, Controller pattern. Preferably, the initial servlet is the Controller, the Java Beans are the Model, and the JSP is the View. Preferred frameworks include an Error Framework, a Logging and Tracing Framework, a Connection Framework, a Reference Data Framework, a Security Framework, and an International Framework.

Abstract: A device for carrying a coat about the person, without wearing the coat, comprises an open-ended tube made of thin foldable material, and a link at each end of the tube, to enable the tube containing a coat, to be carried using a belt or strap. The coat is snugly received within the tube arranged such that the coat lies lengthways within the tube, with the collar end of the coat towards one end of the tube, and the lower edge of the coat towards the other end of the tube. A drawstring may also be provided at one or both ends of the tube. The tube may be integral with the back panel of the coat, wherein the material that makes up the tube, which may be the back panel of the coat itself, is initially laid flat, and when it is required to carry the coat, the coat is turned inside-out, rolled into a tube and fastened.

Abstract: The present invention is a method of evolving classifier programs for signal processing and control. The present invention uses an ‘evolver’ program examine a large number of potential features, which may be from multiple signals to create a ‘classifier’ program. The output of the classifier program is compared to the desired output. One or more classifier programs is then created and optimized by the evolver program by means of genetic programming. The desired output is again compared to actual classifier program output and the difference is used as a measure of fitness to guide the evolution of the classifier program. The optimized classifier program produced by the present invention is fitter than the background art at correctly providing a repeatable and accurate output, especially for complex and simultaneous input signals.

Abstract: A primary PCI bus and multiple secondary PCI busses of a PCI expansion card interface, are interconnected by a routing circuit. The routing circuit functions as a switched bridge between the primary PCI bus and each of the secondary PCI busses, respectively, by associating each secondary PCI bus with an address range, and forwarding a command received from the primary PCI bus to a secondary PCI bus mapped to an address range including the address of the command. Furthermore, the routing circuit forwards commands intended for the primary PCI bus from the secondary PCI busses. In addition, the routing circuit directly routes commands between the secondary PCI busses, when commands received from one secondary PCI bus are intended for another PCI bus, without use of the primary bus. As a result, traffic and latency on the primary PCI bus is reduced and efficiency is increased.

Abstract: An input/output bus architecture that includes: an input/output bus; an input/output device connected to the input/output bus; a main processor, connected to the input/output bus, for executing a device driver corresponding to the input/output device, the device driver generating load/store commands for the input/output device; and a load/store assist engine, connected to the input/output bus and yet independent of the main processor, for loading/storing data to/from the input/output device according to the load/store commands from the device driver. The load/store assist engine decouples the main processor from latencies associated with execution of the load/store commands. The device driver is reassigned to the main processor, rather than being found in a device that is external to the main processor, such as an input/output processor.

Abstract: An externally adjustable dampening control for a shock absorber provides the ability to adjust the hardness and softness of the ride near the normal curb/ride height, and still give strong resistance, and hence control, when the piston moves beyond the intermediate region. The adjustable dampening control includes a bypass for permitting fluid to bypass the piston when the piston is within an intermediate region of the cylinder corresponding to the normal curb/ride height of the shock. The bypass includes a valve body extending longitudinally along a portion of the hollow cylinder and defining a flow passage having first and second longitudinally spaced ports opening to cylinder and defining a flow passage having first and second longitudinally spaced ports opening to the internal chamber. Resistance to piston movement can be adjusted by rotating a knob to move a second piston into and out of the flow passage, thereby adjusting the amount of fluid that can flow through the bypass flow passage.

Abstract: A method, device and system for configuring multifunction I/O device adapters connected to a bus utilizes a slot owner configuration register to identify the ownership of each function slot within the multi-function I/O device adapter. An intelligent I/O device adapter or controller within the multi-function I/O device adapter may control other I/O adapters located in other function slots through the information provided in the slot owner configuration register. Ownership of each slot is initially set, upon power up, to the host unit or processor complex. Thereafter, each intelligent I/O device adapter or controller determines the presence of adapters at other function slots to be controlled, and records this information in the slot owner configuration register.

Abstract: An interrupt and message batching apparatus and method reduces the number and frequency of processor interrupts and resulting context switches by grouping I/O completion events together with a single processor interrupt in a manner that balances I/O operation latency requirements with processor utilization requirements to optimize overall computer system performance. The invention sends a message from a processor complex to an I/O adapter on an I/O bus commanding an I/O device connected to the I/O adapter to perform a function. Upon completion of the commanded function, the message processor in the I/O adapter generates a message and sends it to the processor complex on the I/O bus. The message is enqueued in the message queue of the memory, a message count is updated, and processor complex interrupt is signalled if and when the message count exceeds a message pacing count.

Abstract: An apparatus, system and method permitting a variety of reset procedures and corresponding reset states. A device reset control register is provided for each I/O device adapter in single function or multifunction devices. The device reset control registers permit a greater degree of control over single function devices, multifunction device as a whole and individual device functions within a multifunction device. A device immediate status register synchronizes the various reset procedures. A logical power on reset procedure, a directed unit reset procedure and a directed interface reset procedure utilize the greater degree of control that the device reset control registers provide to force the I/O device adapter, single function device or multifunction device into a corresponding logical power on reset state, a directed unit reset state or a directed interface reset state.

Abstract: An apparatus, system and method permitting dynamic configuration of I/O device adapters connected to a bus utilizes a function configuration register to store a READY/NOT READY status for each of the I/O device adapters. Upon the occurrence of a reset condition, dynamic configuration decision logic detects which I/O device adapters are connected to the bus, determines configuration parameters for each connected I/O device adapter, initializes the configuration space for each connected I/O device adapter, and then sets a corresponding flag in the function configuration register to indicate ready status. An I/O device driver interrupts a configuration process to examine the function configuration register. If ready status can be confirmed from this function configuration register within a time out period, then the configuration process may proceed; otherwise, a device error recovery process is initiated.

Abstract: An I/O system including a processor complex and system main memory connected to I/O adapters via I/O adapters and I/O bus. A message transport mechanism and method stores an upstream message queue and a downstream message queue in system main memory. Queue addresses are stored both in system main memory and designated registers of I/O adapters. The I/O adapters utilize the queue addresses to manage the transfer of downstream command messages and to send upstream response messages to the system main memory via direct memory access across the I/O bus.

Abstract: A two-terminal fuse-antifuse structure comprises a horizontal B-fuse portion and a vertical A-fuse portion disposed between two metallization layers of an integrated circuit device. The two-terminal fuse-antifuse can be programmed with a relatively high current applied across the two terminals to blow the B-fuse, or with a high voltage applied across the two terminals to program the A-fuse. Such a device, connected between two circuit nodes, initially does not provide an electrical connection between the two circuit nodes. It may then be programmed with a relatively high voltage to blow the A-fuse, causing it to conduct between the two circuit nodes. Then, upon application of a relatively high current between the two circuit nodes, the B-fuse will blow, making the device permanently non-conductive.