Abstract: A method of forming a capacitor includes forming first and second capacitor electrodes over a substrate. A capacitor dielectric region is formed intermediate the first and second capacitor electrodes, and includes forming a silicon nitride comprising layer over the first capacitor electrode. A silicon oxide comprising layer is formed over the silicon nitride comprising layer. The silicon oxide comprising layer is exposed to an activated nitrogen species generated from a nitrogen-containing plasma effective to introduce nitrogen into at least an outermost portion of the silicon oxide comprising layer. Silicon nitride is formed therefrom effective to increase a dielectric constant of the dielectric region from what it was prior to said exposing. Capacitors and methods of forming capacitor dielectric layers are also disclosed.

Abstract: Titanium boride (TiBx), zirconium boride (ZrBx) and hafnium boride (HfBx) barriers and electrodes for cell dielectrics for integrated circuits, particularly for DRAM cell capacitors. The barriers protect cell dielectrics from diffusion and other interaction with surrounding materials during subsequent thermal processing.

Abstract: An intermediate metal plug is used to raise the platform to which contact is to be made. In the illustrated process, a partial bit line plug is formed adjacent a stacked capacitor, and an interlevel dielectric formed over the capacitor. The bit line contact is completed by extending a via from the bit line, formed above the interlevel dielectric, down to the level of the intermediate plug, and the via is filled with metal. The height of the via to be filled is thus reduced by the height of the intermediate plug. In one embodiment, the intermediate plug is slightly shorter than an adjacent container-shaped capacitor. In another embodiment, the intermediate plug is about as high as an adjacent stud capacitor.

Abstract: An exemplary embodiment of the present invention discloses a method for forming a storage capacitor for a memory device, by the steps of: forming a bottom electrode of the storage capacitor over a BoroPhosphoSilicate Glass (BPSG) layer; forming a storage capacitor dielectric layer over the bottom electrode, the storage capacitor dielectric layer consisting of a nitride layer that is 50 Åor less in thickness; exposing the nitride dielectric layer to heat during a first stage rapid thermal oxidation step at a first temperature range that is equal to or greater than a reflow temperature required to reflow the BPSG layer; exposing the nitride dielectric layer to wet oxidation during a second stage rapid thermal oxidation step, the second stage rapid thermal oxidation step is performed at a second temperature ranging from 810° C. to 1040° C.

Abstract: An intermediate metal plug is used to raise the platform to which contact is to be made. In the illustrated process, a partial bit line plug is formed adjacent a stacked capacitor, and an interlevel dielectric formed over the capacitor. The bit line contact is completed by extending a via from the bit line, formed above the interlevel dielectric, down to the level of the intermediate plug, and the via is filled with metal. The height of the via to be filled is thus reduced by the height of the intermediate plug. In one embodiment, the intermediate plug is slightly shorter than an adjacent container-shaped capacitor. In another embodiment, the intermediate plug is about as high as an adjacent stud capacitor.

Abstract: A method of forming a high dielectric oxide film conventionally formed using a post formation oxygen anneal to reduce the leakage current of such film includes forming a high dielectric oxide film on a surface. The high dielectric oxide film has a dielectric constant greater than about 4 and includes a plurality of oxygen vacancies present during the formation of the film. The high dielectric oxide film is exposed during the formation thereof to an amount of atomic oxygen sufficient for reducing the number of oxygen vacancies and eliminating the post formation oxygen anneal of the high dielectric oxide film. Further, the amount of atomic oxygen used in the formation method may be controlled as a function of the amount of oxygen incorporated into the high dielectric oxide film during the formation thereof or be controlled as a function of the concentration of atomic oxygen in a process chamber in which the high dielectric oxide film is being formed.

Abstract: A method used during the formation of a semiconductor device comprises providing a wafer substrate assembly comprising a plurality of digit line plug contact pads and capacitor storage cell contact pads which contact a semiconductor wafer. A dielectric layer is provided over the wafer substrate assembly and etched to expose the digit line plug contact pads, and a liner is provided in the opening. A portion of the digit line plug is formed, then the dielectric layer is etched again to expose the capacitor storage cell contact pads. A capacitor bottom plate is formed to contact the storage cell contact pads, then the dielectric layer is etched a third time using the liner and the bottom plate as an etch stop layer. A capacitor cell dielectric layer and capacitor top plate is formed which provides a double-sided container cell. An additional dielectric layer is formed, then the additional dielectric layer, cell top plate, and the cell dielectric are etched to expose the digit line plug portion.

Abstract: An intermediate metal plug is used to raise the platform to which contact is to be made. In the illustrated process, a partial bit line plug is formed adjacent a stacked capacitor, and an interlevel dielectric formed over the capacitor. The bit line contact is completed by extending a via from the bit line, formed above the interlevel dielectric, down to the level of the intermediate plug, and the via is filled with metal. The height of the via to be filled is thus reduced by the height of the intermediate plug. In one embodiment, the intermediate plug is slightly shorter than an adjacent container-shaped capacitor. In another embodiment, the intermediate plug is about as high as an adjacent stud capacitor.

Abstract: A method of fabricating a semiconductor device includes depositing a dielectric film and subjecting the dielectric film to a wet oxidation in a rapid thermal process chamber. The technique can be used, for example, in the formation of various elements in an integrated circuit, including gate dielectric films as well as capacitive elements. The tight temperature control provided by the RTP process allows the wet oxidation to be performed quickly so that the oxidizing species does not diffuse significantly through the dielectric film and diffuse into an underlying layer. In the case of capacitive elements, the technique also can help reduce the leakage current of the dielectric film without significantly reducing its capacitance.

Abstract: A method of forming a high dielectric oxide film includes forming a high dielectric oxide film on a surface. The high dielectric oxide film has a dielectric constant greater than about 4 and includes a plurality of oxygen vacancies present during the formation of the film. The high dielectric oxide film is exposed during the formation thereof to an amount of atomic oxygen sufficient for reducing the number of oxygen vacancies. Further, the amount of atomic oxygen used in the formation method may be controlled as a function of the amount of oxygen incorporated into the high dielectric oxide film during the formation thereof or be controlled as a function of the concentration of atomic oxygen in a process chamber in which the high dielectric oxide film is being formed. An apparatus for forming the high dielectric oxide film is also described.

Abstract: In one aspect, the invention includes a method of semiconductive wafer processing comprising forming a silicon nitride layer over a surface of a semiconductive wafer, the silicon nitride layer comprising at least two portions, one of said at least two portions generating a compressive force against the other of the at least two portions, and the other of the at least two portions generating a tensile force against the one of the at least two portions.

Abstract: A method for forming a storage capacitor for a memory device, by the steps of: forming a bottom electrode of the storage capacitor over a BoroPhosphoSilicate Glass (BPSG) layer; forming a storage capacitor dielectric layer over the bottom electrode, the storage capacitor dielectric layer consisting of a nitride layer that is 50 Å or less in thickness; exposing the nitride dielectric layer to heat during a first stage rapid thermal oxidation step at a first temperature range that is equal to or greater than a reflow temperature required to reflow the BPSG layer; exposing the nitride dielectric layer to wet oxidation during a second stage rapid thermal oxidation step, the second stage rapid thermal oxidation step is performed at a second temperature ranging from 810° C. to 1040° C. and for a time duration of less than three minutes and being sufficient to oxidize the nitride dielectric layer to prevent the diffusion of 90% of oxygen atoms through the nitride dielectric layer.

Abstract: A capacitor having a double sided electrode for enhanced capacitance. In one embodiment, the double sided electrode capacitor is a stacked container capacitor used in a dynamic random access memory circuit. The double sided electrode is preferably formed of a conductive metal, provided that an oxide of the metal is conductive. The double sided electrode capacitor provides a capacitor that has high storage capacitance which provides an increased efficiency for a cell without an increase in the size of the cell.

Abstract: A process used during the formation of a semiconductor device comprises the steps of placing a plurality of semiconductor wafers each having a surface into a chamber of a batch wafer processor such as a diffusion furnace. The wafers are heated to a temperature of between about 300° C. and about 550° C. With the wafers in the chamber, at least one of ammonia and hydrazine is introduced into the chamber, then a precursor comprising trimethylethylenediamine tris(dimethylamino)titanium and/or triethylaluminum is introduced into the chamber. In the chamber, a layer comprising aluminum nitride is simultaneously formed over the surface of each wafer. The inventive process allows for the formation of aluminum nitride or titanium aluminum nitride over the surface of a plurality of wafers simultaneously. A subsequent anneal of the aluminum nitride layer or the titanium aluminum nitride layer can be performed in situ.

Abstract: In one aspect, the invention includes a method of semiconductive wafer processing comprising forming a silicon nitride layer over a surface of a semiconductive wafer, the silicon nitride layer comprising at least two portions, one of said at least two portions generating a compressive force against the other of the at least two portions, and the other of the at least two portions generating a tensile force against the one of the at least two portions.

Abstract: A process for forming a storage capacitor for a semiconductor assembly, by forming a first storage electrode having a top surface consisting of titanium nitride; forming a barrier layer directly on the titanium nitride, the barrier layer (a material containing any one of amorphous silicon, tantalum, titanium, or strontium) being of sufficient thickness to substantially limit the oxidation of the titanium nitride when the semiconductor assembly is subjected to an oxidizing agent (either an oxidizing agent or an nitridizing agent); converting a portion of the barrier layer to a dielectric compound; depositing a storage cell dielectric directly on the dielectric compound, the storage cell dielectric being of the same chemical makeup as the dielectric compound and thereby using the dielectric compound as a nucleation surface; and forming a second capacitor electrode on the storage cell dielectric.

Abstract: Titanium boride (TiBx), zirconium boride (ZrBx) and hafnium boride (HfBx) barriers and electrodes for cell dielectrics for integrated circuits, particularly for DRAM cell capacitors. The barriers protect cell dielectrics from diffusion and other interaction with surrounding materials during subsequent thermal processing.

Abstract: Capacitor constructions and methods of forming the same are described. In one implementation, a capacitor container is formed over a substrate and includes an internal surface and an external surface. At least some of the external surface is provided to be rougher than at least some of the internal container surface. A capacitor dielectric layer and an outer capacitor plate layer are formed over at least portions of the internal and the external surfaces of the capacitor container. In another implementation, a layer comprising roughened polysilicon is formed over at least some of the external container surface but not over any of the internal container surface. In a preferred aspect, the roughened external surface or roughened polysilicon comprises hemispherical grain polysilicon.

Abstract: An intermediate metal plug is used to raise the platform to which contact is to be made. In the illustrated process, a partial bit line plug is formed adjacent a stacked capacitor, and an interlevel dielectric formed over the capacitor. The bit line contact is completed by extending a via from the bit line, formed above the interlevel dielectric, down to the level of the intermediate plug, and the via is filled with metal. The height of the via to be filled is thus reduced by the height of the intermediate plug. In one embodiment, the intermediate plug is slightly shorter than an adjacent container-shaped capacitor. In another embodiment, the intermediate plug is about as high as an adjacent stud capacitor.

Abstract: A method of fabricating a semiconductor device includes depositing a dielectric film and subjecting the dielectric film to a wet oxidation in a rapid thermal process chamber. The technique can be used, for example, in the formation of various elements in an integrated circuit, including gate dielectric films as well as capacitive elements. The tight temperature control provided by the RTP process allows the wet oxidation to be performed quickly so that the oxidizing species does not diffuse significantly through the dielectric film and diffuse into an underlying layer. In the case of capacitive elements, the technique also can help reduce the leakage current of the dielectric film without significantly reducing its capacitance.