Abstract: One embodiment of the present invention provides a system that generates a clock signal within an integrated circuit. This system includes four clocking elements organized into a ring, wherein each clocking element includes at least one input and at least one output, and wherein a signal at an input is complemented at a corresponding output. These clocking elements are spatially distributed throughout the integrated circuit, so that each clocking element provides the clock signal to a different region of the integrated circuit. These clocking elements are also coupled together though a plurality of interconnections, so that each output of each clocking element is coupled to at least one input of a neighboring clocking element. Furthermore, a given signal is inverted an odd number of times in traversing a closed path beginning and ending at any output of any of the four clocking elements and passing through a neighboring clocking element.

Abstract: One embodiment of the present invention provides a system for controlling asynchronous data transfers within a circuit. This system operates by monitoring a first voltage level on a first conductor that specifies whether a first stage of the circuit contains data. The system also monitors a second voltage level on a second conductor that specifies whether a second stage of the circuit contains data. Upon detecting that the first voltage level indicates that first stage contains data to be transmitted to the second stage, and that the second voltage level indicates that the second stage does not contain data, and is therefore available to receive data from the first stage, the system transfers the data from the first stage to the second stage. This is accomplished by generating a second stage latch signal to latch data into the second stage from the first stage.

Abstract: A Muller C-element comprises two stages. The first stage consists of a NAND and a NOR gate, each driven by all of the inputs to the Muller C-element. In the second stage, the outputs of the two gates are used separately to switch on and off two output transistors, which drive the output of the Muller C-element A keeper flip flop serves to retain the output value between changes. Because current from each gate is applied only to one output transistor, delay is reduced. Furthermore, an unneeded output transistor is switched off as soon as logically possible, often during the otherwise unused interval while the input values differ, which reduces both delay and crossover current. In a preferred embodiment, the NAND and NOR gates each comprise a set of series transistors and a set of parallel transistors.

Abstract: One embodiment of the present invention provides a system that generates a clock signal within an integrated circuit. This system includes four clocking elements organized into a ring, wherein each clocking element includes at least one input and at least one output, and wherein a signal at an input is complemented at a corresponding output. These clocking elements are spatially distributed throughout the integrated circuit, so that each clocking element provides the clock signal to a different region of the integrated circuit. These clocking elements are also coupled together though a plurality of interconnections, so that each output of each clocking element is coupled to at least one input of a neighboring clocking element. Furthermore, a given signal is inverted an odd number of times in traversing a closed path beginning and ending at any output of any of the four clocking elements and passing through a neighboring clocking element.

Abstract: An oscillator circuit having a topology that provides for high-speed oscillation in an even number of phases. The topology generally comprises an even number of inverting circuit elements generally including a keeper and an even number of inverters. The circuit elements are connected such that each output of each circuit element is coupled to at least one input of a neighboring circuit element such that a signal traversing a closed path is inverted an odd number of times. One oscillator is implemented using circuit elements containing a keeper having two nodes and two pairs of inverters. The outputs of one pair of inverters are tied to a first node of the keeper and the outputs of the other pair are tied to a second node. In a preferred embodiment, the oscillator circuit contains four such circuit elements arranged in a ring such that the outputs of each circuit element are coupled to the two neighbor circuit elements.

Abstract: The selector circuit rapidly steers an event from a single input to one of two outputs depending on the binary value of a data signal controlling the selector, where events are received at an event input. A selection value, placed at a control input causes the selector circuit to steer the event to one of the outputs. For each change of value at the event input, one or the other of the outputs will change. Which output changes is determined by the selection value applied to the control input. The selector circuit uses variable or dynamic capacitances at the outputs to control which one of the outputs changes in response to an input event. Each node of the selector circuit includes a true line and a complement line. Pass gates are used to either couple the true lines of the outputs together or to couple the true line of each output and the complement line of the other output.

Abstract: The selector circuit rapidly steers an event from a single input to one of two outputs depending on the binary value of a data signal controlling the selector, where events are received at an event input. A selection value, placed at a control input causes the selector circuit to steer the event to one of the outputs. For each change of value at the event input, one or the other of the outputs will change. Which output changes is determined by the selection value applied to the control input. The selector circuit uses variable or dynamic capacitances at the outputs to control which one of the outputs changes in response to an input event. Each node of the selector circuit includes a true line and a complement line. Pass gates are used to either couple the true lines of the outputs together or to couple the true line of each output and the complement line of the other output.

Abstract: A system for distributing clock signals to multiple locations on a chip with minimal skew is disclosed. A series of FIFO control structures, connected in a ring by signal lines of substantially equal length, generates multiple clock signals of equal phase and frequency. The oscillation frequency of the FIFO control ring may be increased to accommodate higher-speed chips, while maintaining synchronization of clock pulses at each stage of the FIFO control ring.

Abstract: Apparatus is disclosed for asynchronously controlling a pipeline. The control circuitry includes an alternating chain of control circuits and detection circuits. When a full control circuit precedes an empty control circuit in the chain, indicating that the data storage element corresponding to the full control circuit should transfer its data to the next storage element corresponding to the empty control circuit, the detection circuit generates a "move" signal. The "move" signal sets the preceding control circuit to empty and the following control circuit to full, thereby enabling movement of a data element from the preceding to the following stage. Because the control circuits are relatively simple and have predictable signal propagation times, the relative reactions of two adjacent control circuits to the common move signal can be tightly controlled. The control circuitry may control a counterflow pipeline, a forking pipeline, or a merging pipeline.

Abstract: The invention provides a method for detecting a call progress tone on a pair of telephone conductors (the telephone line). The level of energy stored in an energy storage device is continually checked. When the level of energy of the energy storage device is below a threshold, the system couples the telephone line to an off-hook impedance. While coupled to the telephone line, the system charges the energy storage device using current drawn from the telephone line, and the system detects the presence of the call progress tone on the telephone line.