Patents by Inventor Scott S. Roth

Scott S. Roth has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10199339
    Abstract: A packaged semiconductor device is made by forming a conductive pad on an external surface of an integrated circuit device, forming a passivation layer over the conductive pad, removing a portion of the passivation layer over a bond area on the conductive pad, forming a sacrificial anode around a majority of a periphery surrounding the bond area, forming a conductive bond in the bond area, and forming an encapsulating material around the conductive bond and an exposed portion of the sacrificial anode.
    Type: Grant
    Filed: July 20, 2016
    Date of Patent: February 5, 2019
    Assignee: NXP USA, Inc.
    Inventors: Sheila F. Chopin, Min Ding, Varughese Mathew, Scott S. Roth
  • Publication number: 20160329288
    Abstract: A packaged semiconductor device is made by forming a conductive pad on an external surface of an integrated circuit device, forming a passivation layer over the conductive pad, removing a portion of the passivation layer over a bond area on the conductive pad, forming a sacrificial anode around a majority of a periphery surrounding the bond area, forming a conductive bond in the bond area, and forming an encapsulating material around the conductive bond and an exposed portion of the sacrificial anode.
    Type: Application
    Filed: July 20, 2016
    Publication date: November 10, 2016
    Inventors: SHEILA F. CHOPIN, MIN DING, VARUGHESE MATHEW, SCOTT S. ROTH
  • Patent number: 9412709
    Abstract: A packaged semiconductor device is made by forming a conductive pad on an external surface of an integrated circuit device, forming a passivation layer over the conductive pad, removing a portion of the passivation layer over a bond area on the conductive pad, forming a sacrificial anode around a majority of a periphery surrounding the bond area, forming a conductive bond in the bond area, and forming an encapsulating material around the conductive bond and an exposed portion of the sacrificial anode.
    Type: Grant
    Filed: May 21, 2013
    Date of Patent: August 9, 2016
    Assignee: FREESCALE SEMICONDUCTOR, INC.
    Inventors: Sheila F. Chopin, Min Ding, Varughese Mathew, Scott S. Roth
  • Publication number: 20140346663
    Abstract: A packaged semiconductor device is made by forming a conductive pad on an external surface of an integrated circuit device, forming a passivation layer over the conductive pad, removing a portion of the passivation layer over a bond area on the conductive pad, forming a sacrificial anode around a majority of a periphery surrounding the bond area, forming a conductive bond in the bond area, and forming an encapsulating material around the conductive bond and an exposed portion of the sacrificial anode.
    Type: Application
    Filed: May 21, 2013
    Publication date: November 27, 2014
    Inventors: Sheila F. Chopin, Min Ding, Varughese Mathew, Scott S. Roth
  • Patent number: 8824114
    Abstract: A circuit comprises a first conductor, a second conductor, and a first detect and disconnect circuit. The first conductor is coupled to a first power supply voltage terminal. The second conductor is positioned a first predetermined distance from the first conductor. The first detect and disconnect circuit has a first terminal coupled to the second conductor and a second terminal coupled to a second power supply voltage terminal. The first detect and disconnect circuit detects a first electrical property change between the second conductor and the first conductor. In response to detecting the change in the first electrical property, the second conductor is disconnected from the second power supply voltage terminal. A method for manufacturing a semiconductor device comprising the circuit is also provided.
    Type: Grant
    Filed: April 21, 2010
    Date of Patent: September 2, 2014
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Jason C. Perkey, Scott S. Roth, Tim J. Zoerner
  • Publication number: 20110261491
    Abstract: A circuit comprises a first conductor, a second conductor, and a first detect and disconnect circuit. The first conductor is coupled to a first power supply voltage terminal. The second conductor is positioned a first predetermined distance from the first conductor. The first detect and disconnect circuit has a first terminal coupled to the second conductor and a second terminal coupled to a second power supply voltage terminal. The first detect and disconnect circuit detects a first electrical property change between the second conductor and the first conductor. In response to detecting the change in the first electrical property, the second conductor is disconnected from the second power supply voltage terminal. A method for manufacturing a semiconductor device comprising the circuit is also provided.
    Type: Application
    Filed: April 21, 2010
    Publication date: October 27, 2011
    Inventors: JASON C. PERKEY, Scott S. Roth, Tim J. Zoerner
  • Patent number: 7741195
    Abstract: A method includes providing a wafer having a first die and a scribe grid, where the first die has die circuitry and a bond pad electrically connected to the die circuitry, and where the scribe grid has a scribe grid pad electrically connected to the die circuitry. The method further includes accessing the scribe grid pad to stimulate the die circuitry. A wafer includes a first die. The first die includes die circuitry, a plurality of conductive layers, and a bond pad electrically connected to the die circuitry via at least one conductive layer of the plurality of conductive layers. The wafer includes a scribe grid having a scribe grid pad, and an interconnect electrically connecting the scribe grid pad to the die circuitry. The plurality of die of the wafer can then be singulated, and at least one of the singulated die can be packaged.
    Type: Grant
    Filed: May 26, 2006
    Date of Patent: June 22, 2010
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Mohammed K. Rashid, Mahbub M. Rashed, Scott S. Roth
  • Publication number: 20070275539
    Abstract: A method includes providing a wafer having a first die and a scribe grid, where the first die has die circuitry and a bond pad electrically connected to the die circuitry, and where the scribe grid has a scribe grid pad electrically connected to the die circuitry. The method further includes accessing the scribe grid pad to stimulate the die circuitry. A wafer includes a first die. The first die includes die circuitry, a plurality of conductive layers, and a bond pad electrically connected to the die circuitry via at least one conductive layer of the plurality of conductive layers. The wafer includes a scribe grid having a scribe grid pad, and an interconnect electrically connecting the scribe grid pad to the die circuitry. The plurality of die of the wafer can then be singulated, and at least one of the singulated die can be packaged.
    Type: Application
    Filed: May 26, 2006
    Publication date: November 29, 2007
    Inventors: Mohammed K. Rashid, Mahbub M. Rashed, Scott S. Roth
  • Patent number: 6285073
    Abstract: The horizontal surface area required to contact semiconductor devices, in integrated circuits fabricated with trench isolation, is minimized without degrading contact resistance by utilizing the vertical surface area of the trench sidewall. A trench isolation region (40) is formed within the semiconductor substrate (12). A doped region (74, 96) is then formed such that it abuts the trench sidewall (24). A portion (56, 110) of the trench sidewall (24), abutting the doped region (74, 96), is then exposed by forming a recess (55, 112) within the trench isolation region (40). A conductive member (66, 114, 118) is then formed such that it is electrically coupled to the doped region (74, 96) along the exposed trench sidewall, as well as along the major surface (13) of the semiconductor substrate (12), and results in the formation of a low resistance contact structure.
    Type: Grant
    Filed: May 30, 1995
    Date of Patent: September 4, 2001
    Inventors: Kent J. Cooper, Scott S. Roth
  • Patent number: 5814868
    Abstract: The present invention includes a transistor having a channel region with a first and second section, wherein the sections have lengths that generally perpendicular to one another. The prevent invention also includes the transistor in an SRAM cell and processes for forming the transistor and the SRAM cell. In the embodiments that are described, the first section has a length that is generally vertical and the second section has a length that is generally extends in a lateral direction. The first section may be an undoped or lightly doped portion of a silicon plug. The plug may be formed including an etching or polishing step.
    Type: Grant
    Filed: September 2, 1994
    Date of Patent: September 29, 1998
    Assignee: Motorola, Inc.
    Inventors: Scott S. Roth, William C. McFadden, Alexander J. Pepe
  • Patent number: 5616941
    Abstract: A floating gate (51)is formed to have a cavity (52) that increases the capacitive coupling between the floating gate (51) and a control gate for the memory cell. The memory cell may be used in EPROM, EEPROM, and flash EEPROM arrays and may be programmed and erased by hot carrier injection, Fowler-Nordheim tunneling or the like. The process sequence for forming the cavity (52) of the floating gate (51) has good process margin allowing some lithographic misalignment. In one embodiment, a multi-tiered floating gate may be formed. The multi-tier structure allows the capacitive coupling to further increase without occupying more area.
    Type: Grant
    Filed: September 20, 1995
    Date of Patent: April 1, 1997
    Assignee: Motorola Inc.
    Inventors: Scott S. Roth, Howard C. Kirsch
  • Patent number: 5604159
    Abstract: The horizontal surface area required to contact semiconductor devices, in integrated circuits fabricated with trench isolation, is minimized without degrading contact resistance by utilizing the vertical surface area of the trench sidewall. A trench isolation region (40) is formed within the semiconductor substrate (12). A doped region (74, 96) is then formed such that it abuts the trench sidewall (24). A portion (56, 110) of the trench sidewall (24), abutting the doped region (74, 96), is then exposed by forming a recess (55, 112) within the trench isolation region (40). A conductive member (66, 114, 118) is then formed such that it is electrically coupled to the doped region (74, 96) along the exposed trench sidewall, as well as along the major surface (13) of the semiconductor substrate (12), and results in the formation of a low resistance contact structure.
    Type: Grant
    Filed: January 31, 1994
    Date of Patent: February 18, 1997
    Assignee: Motorola, Inc.
    Inventors: Kent J. Cooper, Scott S. Roth
  • Patent number: 5583360
    Abstract: A method for forming a vertical neuron MOSFET begins by providing a substrate (12). One or more conductive layers (24 and 28) are formed overlying the substrate (12). An opening (32) is formed through a portion of the conductive layers (24 and 28) to form one or more control electrodes from the conductive layers (24 and 28). A floating gate (36, and 38) is formed adjacent each of the control electrodes. A dielectric layer (34) is formed within the opening (32) and between the control electrodes and the floating gate (36, and 38) to provide for capacitive coupling between the control electrodes and the floating gate (36, and 38). The capacitive coupling may be altered for each control electrode via isotropic sidewall etching and other methods. By forming the neuron MOSFET in a vertical manner, a surface area of the neuron MOSFET is reduced when compared to known neuron MOSFET structures.
    Type: Grant
    Filed: August 28, 1995
    Date of Patent: December 10, 1996
    Assignee: Motorola Inc.
    Inventors: Scott S. Roth, William C. McFadden, Alexander J. Pepe
  • Patent number: 5543339
    Abstract: A floating gate (51) is formed to have a cavity (52) that increases the capacitive coupling between the floating gate (51) and a control gate for the memory cell. The memory cell may be used in EPROM, EEPROM, and flash EEPROM arrays and may be programmed and erased by hot carrier injection, Fowler-Nordheim tunneling or the like. The process sequence for forming the cavity (52) of the floating gate (51) has good process margin allowing some lithographic misalignment. In one embodiment, a multi-tiered floating gate may be formed. The multi-tier structure allows the capacitive coupling to further increase without occupying more area.
    Type: Grant
    Filed: August 29, 1994
    Date of Patent: August 6, 1996
    Assignee: Motorola, Inc.
    Inventors: Scott S. Roth, Howard C. Kirsch
  • Patent number: 5538922
    Abstract: A contact is formed in a semiconductor device (10), independent of underlying topography or pitch. In one method of the present invention, an insulating layer (18) is deposited over a semiconductor substrate (12). An etch stop layer (20) is deposited over the insulating layer. A frame structure (22) is formed on the etch stop material and defines at least one contact region (23 and/or 25) within which the etch stop material is exposed. The exposed portions of the etch stop material are removed from the contact region to expose a portion of the insulating layer. The exposed portion of the insulating layer is then anisotropically etched and at least one contact (30 and/or 32) is formed in the contact region. Depending on where the contact region is positioned, either a self-aligned contact or a non-self-aligned contact may be formed, or both types of contacts may be formed simultaneously.
    Type: Grant
    Filed: January 25, 1995
    Date of Patent: July 23, 1996
    Assignee: Motorola, Inc.
    Inventors: Kent J. Cooper, Jung-Hui Lin, Scott S. Roth, Bernard J. Roman, Carlos A. Mazure, Bich-Yen Nguyen, Wayne J. Ray
  • Patent number: 5480820
    Abstract: A method for forming a vertical neuron MOSFET begins by providing a substrate (12). One or more conductive layers (24 and 28) are formed overlying the substrate (12). An opening (32) is formed through a portion of the conductive layers (24 and 28) to form one or more control electrodes from the conductive layers (24 and 28). A floating gate (36, and 38) is formed adjacent each of the control electrodes. A dielectric layer (34) is formed within the opening (32) and between the control electrodes and the floating gate (36, and 38) to provide for capacitive coupling between the control electrodes and the floating gate (36, and 38). The capacitive coupling may be altered for each control electrode via isotropic sidewall etching and other methods. By forming the neuron MOSFET in a vertical manner, a surface area of the neuron MOSFET is reduced when compared to known neuron MOSFET structures.
    Type: Grant
    Filed: April 17, 1995
    Date of Patent: January 2, 1996
    Assignee: Motorola, Inc.
    Inventors: Scott S. Roth, William C. McFadden, Alexander J. Pepe
  • Patent number: 5455194
    Abstract: A method for the fabrication of a trench isolation region (44) includes the deposition of first, second, and third oxidizable layers (28, 34, 42). The first oxidizable layer (28) is deposited to overlie the surface of a trench (12) formed in a semiconductor substrate (10). The first oxidizable layer (28) also fills a recess (26) formed in a masking layer (14), and resides adjacent to the upper surface of the trench (12). After oxidizing the first oxidizable layer (28), a second oxidizable layer (34) is deposited to fill the trench (12). A third oxidizable layer (42) is deposited to overlie the second oxidizable layer (34) and fills a remaining portion of the recess (26). An oxidation process is performed to oxidize oxidizable layer (42) and a portion of second oxidizable layer (34) to form a trench isolation region (44). In an alternative embodiment of the invention, a shallow isolation region (46) is formed in proximity to the trench isolation region ( 44).
    Type: Grant
    Filed: March 6, 1995
    Date of Patent: October 3, 1995
    Assignee: Motorola Inc.
    Inventors: Barbara Vasquez, Michael P. Masquelier, Scott S. Roth
  • Patent number: 5445107
    Abstract: A silicon-on insulator film (38) is formed by solid phase epitaxial re-growth. A layer of amorphous silicon (36) is formed such that it is only in direct contact with an underlying portion of a silicon substrate (12). The layer of amorphous silicon (36) is subsequently annealed to form a monocrystalline layer of epitaxial silicon (38). Because the amorphous silicon layer (36) is in contact with only the silicon substrate (12), during the re-growth process, the resulting epitaxial layer (38) is formed with a reduced number of crystal defects. The resulting epitaxial silicon layer (38) may then be used to form semiconductor devices.
    Type: Grant
    Filed: November 22, 1993
    Date of Patent: August 29, 1995
    Assignee: Motorola, Inc.
    Inventors: Scott S. Roth, Howard C. Kirsch
  • Patent number: 5374573
    Abstract: A thin film transistor with self-aligned source and drain regions is fabricated, in one embodiment, by forming an opening (124) in a dielectric layer (118) which overlies a substrate (116). A semiconductive sidewall spacer (130) is formed around the perimeter (126) of the opening (124) and adjacent to the sidewall (128) of the opening (124). A first electrode region (120) is electrically coupled to a first portion of the semiconductive sidewall spacer (130) at a first location along the perimeter (126) of the opening (124) which lies only in the second lateral half of the opening (124). A second electrode region (122) is electrically coupled to a second portion of the semiconductive sidewall spacer (130) at a second location along the perimeter (126) of the opening (124) which lies only in the first lateral half of the opening (124). A dielectric layer (132) is formed adjacent to the semiconductive sidewall spacer (130). A control electrode (134) is formed adjacent to the dielectric layer (132).
    Type: Grant
    Filed: February 23, 1994
    Date of Patent: December 20, 1994
    Assignee: Motorola, Inc.
    Inventors: Kent J. Cooper, Scott S. Roth, James D. Hayden, Howard C. Kirsch
  • Patent number: RE35294
    Abstract: A reduction in defects and lateral encroachment is obtained by .[.utilizing a high pressure oxidation in conjunction with.]. an oxidizable layer conformally deposited over an oxidation mask. .[.The.]. .Iadd.In one embodiment, the .Iaddend.use of high pressure oxidation provides for the formation of LOCOS oxide without the formation of defects. Any native oxide present on the substrate surface is removed by using a ramped temperature deposition process to form oxidizable layer and/or a high temperature anneal is performed to remove the native oxide at the substrate surface. In this embodiment, any oxide which can act as a pipe for oxygen diffusion is removed. Therefore, nominal or no lateral encroachment is exhibited..Iadd.Alternately, lateral encroachment can be controlled by intentionally growing an oxide layer on the substrate surface. .Iaddend.
    Type: Grant
    Filed: May 17, 1994
    Date of Patent: July 9, 1996
    Assignee: Motorola, Inc.
    Inventors: Barbara Vasquez, Michael P. Masquelier, Scott S. Roth, Wayne J. Ray