Abstract: The present invention includes a transistor having a channel region with a first and second section, wherein the sections have lengths that generally perpendicular to one another. The prevent invention also includes the transistor in an SRAM cell and processes for forming the transistor and the SRAM cell. In the embodiments that are described, the first section has a length that is generally vertical and the second section has a length that is generally extends in a lateral direction. The first section may be an undoped or lightly doped portion of a silicon plug. The plug may be formed including an etching or polishing step.

Abstract: A thin film transistor with self-aligned source and drain regions is fabricated, in one embodiment, by forming an opening (124) in a dielectric layer (118) which overlies a substrate (116). A semiconductive sidewall spacer (130) is formed around the perimeter (126) of the opening (124) and adjacent to the sidewall (128) of the opening (124). A first electrode region (120) is electrically coupled to a first portion of the semiconductive sidewall spacer (130) at a first location along the perimeter (126) of the opening (124) which lies only in the second lateral half of the opening (124). A second electrode region (122) is electrically coupled to a second portion of the semiconductive sidewall spacer (130) at a second location along the perimeter (126) of the opening (124) which lies only in the first lateral half of the opening (124). A dielectric layer (132) is formed adjacent to the semiconductive sidewall spacer (130). A control electrode (134) is formed adjacent to the dielectric layer (132).

Abstract: A semiconductor device (20) makes contact between a first metal line (22) and an overlying second metal line (24) without the need for a conductive landing pad. Sidewall spacers (30) are formed adjacent sides of metal lines (22) such that during formation of a via (34) in an overlying dielectric layer (32), the sidewall spacer prevent trenching of underlying dielectric layer (28) if the via is misaligned. The sidewall spacers are formed of a dielectric material which has an etch rate which is significantly slower than the etch rate of dielectric layer (32). In another embodiment, portions of the sidewall spacers are selectively removed prior to depositing a second metal layer (42). Upon depositing the second metal layer, the side of metal line (22) is locally clad with the second metal to increase contact area and lowering contact resistance.

Abstract: A method for forming a planarized layer of material starts by providing a substrate (12). An integrated circuit layer (14) is formed overlying the substrate (12). A first layer of material (16) is formed overlying the integrated circuit layer (14). An etch stop layer (18) is formed overlying the layer of material (16) and etched to form sidewall formations or spacers. A second layer of material (20) is formed overlying the layer of material (16) and the etch stop layer (18). Planarization, polishing, or etch-back processing is performed using the etch stop layer (18) to endpoint. The resulting planarized layer has a thickness which is determined accurately by the etch stop layer (18).

Abstract: A method requiring only a single mask results in an isolation oxide (50) which is the same size as, instead of becoming larger than, the dimension originally defined by the lithographic system. A buffer layer (14) is formed over the substrate (12). An oxidation resistant layer (16) is formed over the buffer layer (14). The oxidation resistant layer (16) is etched and a disposable sidewall spacer (30) is formed adjacent to the sidewall of the oxidation resistant layer (28), and a trench region is defined (36). The trench region (36) is etched to form a trench. The disposable sidewall spacer (30) is removed and a conformal layer (48) of oxidizable material is deposited over the trench sidewall (40) and the trench bottom surface (38). The conformal layer (48) is then oxidized to form electrical isolation in the isolation regions (26) of the substrate (12).

Abstract: A contact is formed in a semiconductor device (10), independent of underlying topography or pitch. In one method of the present invention, an insulating layer (18) is deposited over a semiconductor substrate (12). An etch stop layer (20) is deposited over the insulating layer. A frame structure (22) is formed on the etch stop material and defines at least one contact region (23 and/or 25) within which the etch stop material is exposed. The exposed portions of the etch stop material are removed from the contact region to expose a portion of the insulating layer. The exposed portion of the insulating layer is then anisotropically etched and at least one contact (30 and/or 32) is formed in the contact region. Depending on where the contact region is positioned, either a self-aligned contact or a non-self-aligned contact may be formed, or both types of contacts may be formed simultaneously.

Abstract: A semiconductor device and process wherein an ITLDD device (60) is formed having an inverse-T (IT) transistor gate with a variable work function (.PHI.) across the gate. The variable work function is attained by depositing a work function adjusting layer onto the thin gate extensions of the IT-gate. In accordance with one embodiment of the invention, a semiconductor substrate (10) of a first conductivity type is provided having a gate dielectric layer (12) formed thereon. First and second lightly doped regions (36, 37) of a second conductivity type are formed in the substrate which are spaced apart by a channel region (38). An IT-gate electrode (48) is formed on the gate dielectric layer overlying the first and second lightly doped regions and the channel region. The IT-gate has a relatively thick central section (32) and relatively thin lateral extensions (50) projecting from the central portion along the gate dielectric layer.

Abstract: A method of removing undesired ions, such as chlorine, hypochlorite, chromium, cyanide and heavy metal ions, from an aqueous preparation containing one or more of said ions consists of adding to the aqueous preparation an effective amount of magnesium bisulfite to inactivate the undesired ions and then adjusting the pH of the mixture to an appropriate pH. Compositions containing magnesium bisulfite and divalent and trivalent ions are disclosed.

Abstract: A buried contact in a semiconductor device is formed by forming an oxide layer on a surface of a semiconductor substrate. A heavily-doped polysilicon layer is formed over the oxide layer and selectively etched to leave a first portion of the polysilicon layer over the surface and remove a second portion of the polysilicon layer from over the surface. The remaining first portion of polysilicon has a vertical surface which is over the surface of the substrate. After this step there is oxide between the first portion of the polysilicon layer and the substrate. An isotropic etch is performed which removes a portion of the oxide between the first portion of the polysilicon layer and the substrate to leave a void between the first portion of the polysilicon layer and the surface of the substrate from the vertical surface of the first portion of the polysilicon to a predetermined distance from the vertical surface of the first portion of the polysilicon layer.

Abstract: A semiconductor device is disclosed having elevated source and drain regions formed by selectively depositing silicon onto a patterned layer of silicon which acts as a nucleation site for the propagation of the selective deposition process. In accordance with one embodiment of the invention, a silicon substrate is provided of a first conductivity type having an active surface area surrounded by an isolation region. A gate dielectric is formed overlying the active surface area of the substrate and a gate electrode is formed on a central portion of the active surface area. An insulation layer is formed which encapsulates the gate electrode and a first layer of silicon is deposited on the substrate. The first silicon layer is patterned to form a patterned portion overlying the active surface area and the isolation region which is spaced apart from the gate electrode by the insulation layer overlying the gate electrode.

Abstract: A semiconductor device and process wherein an ITLDD device (60) is formed having an inverse-T (IT) transistor gate with a variable work function (.PHI.) across the gate. The variable work function is attained by depositing a work function adjusting layer onto the thin gate extensions of the IT-gate. In accordance with one embodiment of the invention, a semiconductor substrate (10) of a first conductivity type is provided having a gate dielectric layer (12) formed thereon. First and second lightly doped regions (36, 37) of a second conductivity type are formed in the substrate which are spaced apart by a channel region (38). An IT-gate electrode (48) is formed on the gate dielectric layer overlying the first and second lightly doped regions and the channel region. The IT-gate has a relatively thick central section (32) and relatively thin lateral extensions (50) projecting from the central portion along the gate dielectric layer.

Abstract: An improved LOCOS isolation process is disclosed wherein an oxidizable layer is conformably dieposited to overlie a silicon nitride oxidation mask. In accordance with one embodiment of the invention, a composite layer comprising a buffer layer and an oxidation resistant material is patterned to form an oxidation mask on a silicon substrate. A layer of an oxidizable material is conformably deposited to overlie the oxidation mask. During the oxidation process used to form electrical isolation structures in the substrate, a substantial reduction in lateral oxidation encroachment is realized.

Abstract: A method for the prevention of dopant diffusion from the back side of a doped semiconductor substrate during epitaxial layer growth. The entire surface of the substrate is first covered with a cleanly etchable material. Around the entire first layer is formed a second dopant diffusion barrier layer. The front sides of the layers are then selectively etched away to expose the front side of the substrate upon which the epitaxial layer will be grown without contamination of dopant diffusion from the sealed back side of the substrate.