Abstract: The present disclosure relates to methods for making asunaprevir, useful treatment of Hepatitis C virus (HCV) infection, and its intermediates.

Abstract: Processes are described for the preparation of estrogen receptor modulating compound, (E)-3-(4-((E)-2-(2-chloro-4-fluorophenyl)-1-(1H-indazol-5-yl)but-1-en-1-yl)phenyl)acrylic acid I: and salts thereof, and intermediates useful for the preparation of I.

Abstract: A method for producing HIV maturation inhibitor compound is set forth using betulin as starting material, and utilizing Lossen rearrangement techniques.

Abstract: The present disclosure relates to processes for preparing (cyclopentyl[d]pyrimidin-4-yl)piperazine compounds, and more particularly relates to processes for preparing (R)-4-(5-methyl-7-oxo-6,7-dihydro-5H-cyclopenta[d] pyrimidin-4-yl)piperazine and N-protected derivatives thereof, which may be used as an intermediate in the synthesis of Ipatasertib (i.e., (S)-2-(4-chlorophenyl)-1-(4-((5R,7R)-7-hydroxy-5-methyl-6,7-dihydro-5H-cyclopenta[d]pyrimidin-4-yl)piperazin-1-yl)-3-(isopropylamino)-propan-1-one). The present disclosure additionally relates to various compounds that are intermediates employed in these processes.

Abstract: Processes are described for the preparation of estrogen receptor modulating compound, (E)-3-(4-((E)-2-(2-chloro-4-fluorophenyl)-1-(1H-indazol-5-yl)but-1-en-1-yl)phenyl)acrylic acid I: and salts thereof, and intermediates useful for the preparation of I.

Abstract: A voltage multiplier circuit. The voltage multiplier circuit includes a storage element, a first transistor, a second transistor and third transistor. The storage element has a first end and a second end. The second end is coupled to a clock signal input. The first transistor has a gate coupled to a voltage node, a first terminal coupled to a supply node, and a second terminal coupled to the first end of the storage element. A second transistor has a first terminal coupled to the first end of the storage element and a second terminal coupled to the voltage output. The third transistor has a gate in communication with the clock input and a first terminal coupled to the voltage node.

Abstract: A voltage multiplier circuit. The voltage multiplier circuit includes a storage element, a first transistor, a second transistor and third transistor. The storage element has a first end and a second end. The second end is coupled to a clock signal input. The first transistor has a gate coupled to a voltage node, a first terminal coupled to a supply node, and a second terminal coupled to the first end of the storage element. A second transistor has a first terminal coupled to the first end of the storage element and a second terminal coupled to the voltage output. The third transistor has a gate in communication with the clock input and a first terminal coupled to the voltage node.

Abstract: Physical crystal structures of a compound of the formula I: are provided including the free base monohydrate thereof (form H-1) and the hydrochloric acid salt thereof, including hydrochloric acid salt containing 0.75 equivalent of H2O (form H0.75-3) and hydrochloric acid salt containing 2 equivalents of H2O (form H2-1), and hydrochloric acid salt Pattern P-5, preferably in substantially pure form, and other forms as described herein, pharmaceutical compositions containing structures of compound I or IA, processes for preparing same, intermediates used in preparing same, and methods of treating diseases such as diabetes using such structures.

Abstract: Physical crystal structures of a compound of the formula I: are provided including the free base monohydrate thereof (form H-1) and the hydrochloric acid salt thereof, including hydrochloric acid salt containing 0.75 equivalent of H2O (form H0.75-3) and hydrochloric acid salt containing 2 equivalents of H2O (form H2-1), and hydrochloric acid salt Pattern P-5, preferably in substantially pure form, and other forms as described herein, pharmaceutical compositions containing structures of compound I or IA, processes for preparing same, intermediates used in preparing same, and methods of treating diseases such as diabetes using such structures.

Abstract: Physical crystal structures of a compound of the formula I: are provided including the free base monohydrate thereof (form H-1) and the hydrochloric acid salt thereof, including hydrochloric acid salt containing 0.75 equivalent of H2O (form H0.75-3) and hydrochloric acid salt containing 2 equivalents of H2O (form H2-1), and hydrochloric acid salt Pattern P-5, preferably in substantially pure form, and other forms as described herein, pharmaceutical compositions containing structures of compound I or IA, processes for preparing same, intermediates used in preparing same, and methods of treating diseases such as diabetes using such structures.

Abstract: Physical crystal structures of a compound of the formula I: are provided including the free base monohydrate thereof (form H-1) and the hydrochloric acid salt thereof, including hydrochloric acid salt containing 0.75 equivalent of H2O (form H0.75-3) and hydrochloric acid salt containing 2 equivalents of H2O (form H2-1), and hydrochloric acid salt Pattern P-5, preferably in substantially pure form, and other forms as described herein, pharmaceutical compositions containing structures of compound I or IA, processes for preparing same, intermediates used in preparing same, and methods of treating diseases such as diabetes using such structures.

Abstract: Physical crystal structures of a compound of the formula I: are provided including the free base monohydrate thereof (form H-1) and the hydrochloric acid salt thereof, including hydrochloric acid salt containing 0.75 equivalent of H2O (form H0.75-3) and hydrochloric acid salt containing 2 equivalents of H2O (form H2-1), and hydrochloric acid salt Pattern P-5, preferably in substantially pure form, and other forms as described herein, pharmaceutical compositions containing structures of compound I or IA, processes for preparing same, intermediates used in preparing same, and methods of treating diseases such as diabetes using such structures.

Abstract: Physical crystal structures of a compound of the formula I: are provided including the free base monohydrate thereof (form H-1) and the hydrochloric acid salt thereof, including hydrochloric acid salt containing 0.75 equivalent of H2O (form H0.75-3) and hydrochloric acid salt containing 2 equivalents of H2O (form H2-1), and hydrochloric acid salt Pattern P-5, preferably in substantially pure form, and other forms as described herein, pharmaceutical compositions containing structures of compound I or IA, processes for preparing same, intermediates used in preparing same, and methods of treating diseases such as diabetes using such structures.

Abstract: Physical crystal structures of a compound of the formula I: are provided including the free base monohydrate thereof (form H-1) and the hydrochloric acid salt thereof, including hydrochloric acid salt containing 0.75 equivalent of H2O (form H0.75-3) and hydrochloric acid salt containing 2 equivalents of H2O (form H2-1), and hydrochloric acid salt Pattern P-5, preferably in substantially pure form, and other forms as described herein, pharmaceutical compositions containing structures of compound I or IA, processes for preparing same, intermediates used in preparing same, and methods of treating diseases such as diabetes using such structures.

Abstract: A platform application specific integrated circuit (ASIC) including a base layer. The base layer generally comprises a predefined input/output (I/O) region and a predefined core region. The predefined input/output (I/O) region may comprise a plurality of pre-diffused regions disposed in the platform ASIC. The predefined core region may comprise one or more metal layers defining a plurality of power regions formed according to a custom design created after the base layer is fabricated. The base layer can be customized by depositing one or more metal layers.

Abstract: A method for interconnecting sub-functions of metal-mask programmable functions that includes the steps of (A) forming a base layer of a platform application specific integrated circuit (ASIC) comprising a plurality of pre-diffused regions disposed around a periphery of the platform ASIC, (B) forming two or more sub-functions of a function with a metal mask set placed over a number of the plurality of pre-diffused regions of the platform application specific integrated circuit and (C) configuring one or more connection points in each of the two or more sub-functions such that interconnections between the two or more sub-functions are tool routable in a single layer. Each of the pre-diffused regions is configured to be metal-programmable.

Abstract: A method for producing a chip is disclosed. A first step of the method may include fabricating the chip only up to and including a first metal layer such that a core region of the chip has an array of cells, each of the cells having a plurality of transistors. A second step generally involves designing a plurality of upper metal layers above the first metal layer in response to a custom design created after the first fabricating has started, the upper metal layers interconnecting a plurality of the cells to form (i) a mixed-signal module and (ii) a digital module, the mixed signal module generating at least one analog signal and at least one digital signal. In a third step, the method may include fabricating the chip to add the upper metal layers.

Abstract: A method for producing a chip is disclosed. A first step of the method may involve fabricating the chip only up to and including a first metal layer during a first manufacturing phase such that an input/output (I/O) region of the chip has a plurality of slots, where each of the slots has a plurality of first transistors. A second step of the method may involve designing a plurality of upper metal layers above the first metal layer in response to a custom design created after the first fabricating has started, the upper metal layers interconnecting a plurality of the first transistors to form a plurality of mixed-signal building block functions. A third step of the method may involve fabricating the chip to add the upper metal layers during a second manufacturing phase.

Abstract: A method for producing a chip is disclosed. A first step of the method may involve first fabricating the chip only up to and including a first metal layer such that a core region of the chip has an array of cells, each of the cells having a plurality of transistors. A second step of the method may be to design a plurality of upper metal layers above the first metal layer in response to a custom design created after the first fabricating has started, the upper metal layers interconnecting a plurality of the cells to form an electrostatic discharge clamp at a power domain crossing. A third step may include second fabricating the chip to add the upper metal layers.

Abstract: An apparatus including a base layer of a platform application specific integrated circuit (ASIC), a mixed-signal function and a built-in self test (BIST) function. The base layer of the platform ASIC generally includes a plurality of pre-diffused regions disposed around a periphery of the platform ASIC. Each of the pre-diffused regions is generally configured to be metal-programmable. The mixed-signal function may include two or more sub-functions formed with a metal mask set placed over a first number of the plurality of pre-diffused regions. The BIST function may be formed with a metal mask set placed over a second number of the plurality of pre-diffused regions. The BIST function may be configured to test the mixed-signal function and present a digital signal indicating an operating condition of the mixed-signal function.