Abstract: An apparatus that may include a base layer of a platform application specific integrated circuit (ASIC) and a mixed-signal function. The base layer of the platform application specific integrated circuit (ASIC) generally comprises a plurality of pre-diffused regions disposed around a periphery of the platform ASIC. Each of the pre-diffused regions may be configured to be metal-programmable. The mixed-signal function may include two or more sub-functions formed with a metal mask set placed over a number of the plurality of pre-diffused regions.

Abstract: An apparatus comprising an integrated circuit and a logic portion. The integrated circuit may have a plurality of regions each (i) pre-diffused and configured to be metal-programmed and (ii) configured to connect the integrated circuit to a socket. The logic portion may be implemented on the integrated circuit. The plurality of metal programmable regions are each (i) independently programmable and (ii) located in one of said pre-diffused regions. Each of the metal programmable regions comprises (a) a regulator section configured to generate an operating voltage from a common supply voltage, (b) a logic section configured to implement integrated circuit functions and operate at the operating voltage, and (c) a level shifter configured to shift the operating voltage to an external voltage level.

Abstract: An apparatus comprising an integrated circuit having (i) a number of regions each pre-diffused and configured to be metal-programmed and (ii) a plurality of pins configured to connect the integrated circuit to a socket. A logic portion may be implemented on the integrated circuit (i) configured to implement integrated circuit operations and (ii) having one or more I/O connections and one or more supply connections. A first group of the pre-diffused regions are metal-programmed and coupled to said I/O connections. A second group of the pre-diffused regions are metal-programmed and coupled to the supply connections.

Abstract: An apparatus comprising a first transistor pair, second transistor pair, a third transistor pair and a fourth transistor pair. The first transistor pair may be (i) implemented as thin oxide devices and (ii) configured to receive a differential input signal. The second transistor pair may be (i) implemented as thick oxide devices and (ii) configured to generate a differential output signal in response to the differential input signal. The output signal has a voltage higher than the input signal. The third transistor pair may be (i) connected between the first and second transistor pairs and (ii) configured to protect the first transistor pair. The fourth transistor pair may be (i) connected between the third transistor pair and a ground and (ii) configured to increase an operating speed of the apparatus.

Abstract: The invention provides novel inhibitors of hedgehog signaling that are useful as a therapeutic agents for treating malignancies where the compounds have the general formula I: wherein A, X, Y R1, R2, R3, R4, m and n are as described herein.

Abstract: A method and apparatus are provided for measuring high speed glitch energy between first and second. The method and apparatus induce a change in charge on the first node from a first charge level to a second charge level with glitch energy supplied by the second node. An amount of charge is then supplied to the first node to restore the charge on the first node from the second charge level toward the first charge level. A representation of the amount of charge supplied to the first node is measured.

Abstract: A level shifter circuit configured for use between a core of a chip and input/output transistor of the chip in order to shield low voltage devices residing on the core. The level shifter circuit includes voltage tolerant native devices which have VDDCORE on their gates, and each voltage tolerant native device is cascoded with a low voltage transistor on the core.

Abstract: A novel process for the asymmetric synthesis of an amino-pyrrolidinone of the type shown below from appropriate pyrrolidinones is described. These compounds are useful as intermediates for MMP and TACE inhibitors.

Abstract: A level shifter circuit configured for use between a core of a chip and input/output transistors of the chip in order to shield low voltage devices residing on the core. The level shifter circuit includes voltage tolerant native devices which have VDDCORE on their gates, and each voltage tolerant native device is cascoded with a low voltage transistor on the core.

Abstract: A novel process for the asymmetric synthesis of an amino-pyrrolidinone of the type shown below is described.

Abstract: A novel process for the asymmetric synthesis of an amino-pyrrolidinone of the type shown below from appropriate pyrrolidinones is described.

Abstract: A slew based clock multiplier which outputs a fraction of a master clock without having to use, as a reference, an edge of a higher frequency clock, and without having to use precision delay cells to delay edges of the master clock. The slew based clock multiplier can be configured to provide such an output as the result of a ratio of input current sources, a ratio of capacitors in the circuit, or as a result of a combination of the two.

Abstract: A slew based clock multiplier which outputs a fraction of a master clock without having to use, as a reference, an edge of a higher frequency clock, and without having to use precision delay cells to delay edges of the master clock. The slew based clock multiplier can be configured to provide such an output as the result of a ratio of input current sources, a ratio of capacitors in the circuit, or as a result of a combination of the two.