Abstract: A method is described that includes determining a number of program and erase cycles associated with a block of pages of a memory device and determining a preprogram voltage based on the number of program and erase cycles to apply to the block of pages prior to an erase operation. The method further includes applying the preprogram voltage to the block of pages and performing an erase operation on the block of pages following application of the preprogram voltage to the block of pages.

Abstract: A method is described that includes performing a first erase operation on a set of memory cells of a memory device using an erase voltage, which is set to a first voltage value and adjusting the erase voltage to a second voltage value based on feedback from performance of at least the first erase operation. The method further includes performing a second erase operation on the set of memory cells using the erase voltage, which is set to the second voltage value. In this configuration, the erase voltage set to the second voltage value is an initial voltage applied to the set of memory cells to perform erase operations such that each subsequent erase operation on the set of memory cells following the first erase operation uses an erase voltage that is equal to or greater than the second voltage value when erasing the first set of memory cells.

Abstract: A processing device in a memory system detects a data loss occurrence in a block of a memory component. The processing device further designates the block as a quarantined block, performs a stress test on the block, and depending on whether the stress test on the block satisfies a testing criterion, either designates the block as usable by the memory component or retires the block of the memory component.

Abstract: Apparatuses and methods for operating mixed mode blocks. One example method can include tracking single level cell (SLC) mode cycles and extra level cell (XLC) mode cycles performed on the mixed mode blocks, maintaining a mixed mode cycle count corresponding to the mixed mode blocks, and adjusting the mixed mode cycle count differently for mixed mode blocks operated in a SLC mode than for mixed blocks operated in a XLC mode.

Abstract: A processing device in a memory system detects a data loss occurrence in a block of a memory component. The processing device identifies a behavioral criterion associated with the data loss occurrence in the block of the memory component. The processing device further increments a counter associated with the block in response to an occurrence of the behavioral criterion, wherein a value of the counter corresponds to a number of occurrences of a plurality of behavioral criteria associated with data loss occurrences in the block. Responsive to determining that the value of the counter satisfies a first threshold criterion, the processing device designates the block as a quarantined block, performs a stress test of a plurality of stress tests of the block, and responsive to the block failing a first stress test, the processing device retires the block of the memory component.

Abstract: Apparatuses and methods for operating mixed mode blocks. One example method can include tracking single level cell (SLC) mode cycles and extra level cell (XLC) mode cycles performed on the mixed mode blocks, maintaining a mixed mode cycle count corresponding to the mixed mode blocks, and adjusting the mixed mode cycle count differently for mixed mode blocks operated in a SLC mode than for mixed blocks operated in a XLC mode.

Abstract: A processing device in a memory system detects a data loss occurrence in a block of a memory component. The processing device identifies a behavioral criterion associated with the data loss occurrence in the block of the memory component. The processing device further increments a counter associated with the block in response to an occurrence of the behavioral criterion, wherein a value of the counter corresponds to a number of occurrences of a plurality of behavioral criteria associated with data loss occurrences in the block. Responsive to determining that the value of the counter satisfies a first threshold criterion, the processing device designates the block as a quarantined block, performs a stress test of a plurality of stress tests of the block, and responsive to the block failing a first stress test, the processing device retires the block of the memory component.

Abstract: NAND memory devices are described that utilize higher read-margin cell types to provide a more granular read disturb indicator without utilizing dummy cells. For example, a NAND architecture may have some cells that are configured as SLC or MLC cells. SLC or MLC cells have more read disturb margin—that is these cells can withstand more read disturb current leakage into the cell before a bit error occurs than TLC or QLC cells. These higher margin cells may serve as the read disturb indicator for a group of cells that have a comparatively lower read disturb margin. Since there are more pages of these higher margin cells than there are pages of dummy cells, these indicators may serve a smaller group of pages than the dummy pages. This reduces the time needed to complete a read disturb scan as fewer pages need to be scanned.

Abstract: A system associated with detecting a cyber-attack and reconstructing events associated with a cyber-attack campaign, is disclosed. The system performs various operations that include receiving an audit data stream associated with cyber events. The system identifies trustworthiness values in a portion of data associated with the cyber events and assigns provenance tags to the portion of the data based on the identified trustworthiness values. An initial visual representation is generated based on the assigned provenance tags to the portion of the data. The initial visual representation is condensed based on a backward traversal of the initial visual representation in identifying a shortest path from a suspect node to an entry point node. A scenario visual representation is generated that specifies nodes most relevant to the cyber events associated with the cyber-attack based on the identified shortest path. A corresponding method and computer-readable medium are also disclosed.

Abstract: Apparatuses and methods for operating mixed mode blocks. One example method can include tracking single level cell (SLC) mode cycles and extra level cell (XLC) mode cycles performed on the mixed mode blocks, maintaining a mixed mode cycle count corresponding to the mixed mode blocks, and adjusting the mixed mode cycle count differently for mixed mode blocks operated in a SLC mode than for mixed blocks operated in a XLC mode.

Abstract: Apparatuses and methods for operating mixed mode blocks. One example method can include tracking single level cell (SLC) mode cycles and extra level cell (XLC) mode cycles performed on the mixed mode blocks, maintaining a mixed mode cycle count corresponding to the mixed mode blocks, and adjusting the mixed mode cycle count differently for mixed mode blocks operated in a SLC mode than for mixed blocks operated in a XLC mode.

Abstract: NAND memory devices, are described that utilize higher read-margin cell types to provide a more granular read disturb indicator without utilizing dummy cells. For example, a NAND architecture may have some cells that are configured as SLC or MLC cells. SLC or MLC cells have more read disturb margin—that is these cells can withstand more read disturb current leakage into the cell before a bit error occurs than TLC or QLC cells. These higher margin cells may serve as the read disturb indicator for a group of cells that have a comparatively lower read disturb margin. Since there are more pages of these higher margin cells than there are pages of dummy cells, these indicators may serve a smaller group of pages than the dummy pages. This reduces the time needed to complete a read disturb scan as fewer pages need to be scanned.

Abstract: Apparatuses and methods for operating mixed mode blocks. One example method can include tracking single level cell (SLC) mode cycles and extra level cell (XLC) mode cycles performed on the mixed mode blocks, maintaining a mixed mode cycle count corresponding to the mixed mode blocks, and adjusting the mixed mode cycle count differently for mixed mode blocks operated in a SLC mode than for mixed blocks operated in a XLC mode.