Abstract: In some examples, a method comprises: obtaining a substrate having at a metal interconnect layer deposited over the substrate; forming a first dielectric layer on the metal interconnect layer; forming a second dielectric layer on the first dielectric layer; forming a capacitor metal layer on the second dielectric layer; patterning and etching the capacitor metal layer and the second dielectric layer to the first dielectric layer to leave a portion of the capacitor metal layer and the second dielectric layer on the first dielectric layer; forming an anti-reflective coating to cover the portion of the capacitor metal layer and the second dielectric layer, and to cover the metal interconnect layer; and patterning the metal interconnect layer to form a first metal layer and a second metal layer.

Abstract: A method of fabricating an integrated circuit (IC) includes forming a dielectric layer on a substrate having a plurality of the IC. A thin-film resistor (TFR) layer is deposited on the dielectric layer, and an underlayer (UL) including carbon is formed on the TFR layer. A hard mask layer including silicon is formed on the UL. Masked etching of the hard mask layer transfers a pattern of a photoresist layer onto the hard mask layer to form a hard mask layer pattern. Masked etching of the UL transfers the hard mask layer pattern onto the UL to form a UL pattern. Masked etching of the TFR layer transfers the UL pattern onto the TFR layer to form a TFR layer pattern including a matched pair of TFRs. The matched pair of TFRs are generally included in circuitry configured together for implementing at least one function.

Abstract: In some examples, an integrated circuit comprises a substrate; a first metal layer and a second metal layer positioned above the substrate; a first composite dielectric layer located on the first metal layer, wherein the first composite dielectric layer comprises a first anti-reflective coating; a second composite dielectric layer positioned on the second metal layer, wherein the second composite dielectric layer comprises a second anti-reflective coating; and a capacitor metal layer disposed over the first composite dielectric layer.

Abstract: In some examples, an integrated circuit comprises a substrate; a first metal layer and a second metal layer positioned above the substrate; a first composite dielectric layer located on the first metal layer, wherein the first composite dielectric layer comprises a first anti-reflective coating; a second composite dielectric layer positioned on the second metal layer, wherein the second composite dielectric layer comprises a second anti-reflective coating; and a capacitor metal layer disposed over the first composite dielectric layer.

Abstract: A method of fabricating an integrated circuit (IC) includes forming a dielectric layer on a substrate having a plurality of the IC. A thin-film resistor (TFR) layer is deposited on the dielectric layer, and an underlayer (UL) including carbon is formed on the TFR layer. A hard mask layer including silicon is formed on the UL. Masked etching of the hard mask layer transfers a pattern of a photoresist layer onto the hard mask layer to form a hard mask layer pattern. Masked etching of the UL transfers the hard mask layer pattern onto the UL to form a UL pattern. Masked etching of the TFR layer transfers the UL pattern onto the TFR layer to form a TFR layer pattern including a matched pair of TFRs. The matched pair of TFRs are generally included in circuitry configured together for implementing at least one function.

Abstract: In some examples, an integrated circuit comprises a substrate; a first metal layer and a second metal layer positioned above the substrate; a first composite dielectric layer located on the first metal layer, wherein the first composite dielectric layer comprises a first anti-reflective coating; a second composite dielectric layer positioned on the second metal layer, wherein the second composite dielectric layer comprises a second anti-reflective coating; and a capacitor metal layer disposed over the first composite dielectric layer.

Abstract: In some examples, a method comprises: obtaining a substrate having at a metal interconnect layer deposited over the substrate; forming a first dielectric layer on the metal interconnect layer; forming a second dielectric layer on the first dielectric layer; forming a capacitor metal layer on the second dielectric layer; patterning and etching the capacitor metal layer and the second dielectric layer to the first dielectric layer to leave a portion of the capacitor metal layer and the second dielectric layer on the first dielectric layer; forming an anti-reflective coating to cover the portion of the capacitor metal layer and the second dielectric layer, and to cover the metal interconnect layer; and patterning the metal interconnect layer to form a first metal layer and a second metal layer.

Abstract: A method to fabricate a transistor comprises: forming a first dielectric layer on a semiconductor substrate; depositing a barrier layer on the first dielectric layer; depositing an anti-reflective coating on the barrier layer; depositing and exposing a pattern in a photoresist layer to radiation followed by etching to provide an opening; etching a portion of the anti-reflective coating below the opening; etching a portion of the barrier layer below the opening to expose a portion of the first dielectric layer; providing an ambient oxidizing agent to grow an oxide region followed by removing the barrier layer; implanting dopants into the semiconductor substrate after removing the barrier layer; removing the first dielectric layer after implanting dopants into the semiconductor substrate; and forming a second dielectric layer after removing the first dielectric layer, wherein the oxide region is grown to be thicker than the second dielectric layer.

Abstract: A method to fabricate a transistor comprises: forming a first dielectric layer on a semiconductor substrate; depositing a barrier layer on the first dielectric layer; depositing an anti-reflective coating on the barrier layer; depositing and exposing a pattern in a photoresist layer to radiation followed by etching to provide an opening; etching a portion of the anti-reflective coating below the opening; etching a portion of the barrier layer below the opening to expose a portion of the first dielectric layer; providing an ambient oxidizing agent to grow an oxide region followed by removing the barrier layer; implanting dopants into the semiconductor substrate after removing the barrier layer; removing the first dielectric layer after implanting dopants into the semiconductor substrate; and forming a second dielectric layer after removing the first dielectric layer, wherein the oxide region is grown to be thicker than the second dielectric layer.

Abstract: An integrated circuit containing elongated contacts, including elongated contacts which connect to at least three active areas and/or MOS gates, and including elongated contacts which connect to exactly two active areas and/or MOS gates and directly connect to a first level interconnect. A process of forming an integrated circuit containing elongated contacts, including elongated contacts which connect to at least three active areas and/or MOS gates, using exactly two contact photolithographic exposure operations, and including elongated contacts which connect to exactly two active areas and/or MOS gates and directly connect to a first level interconnect.

Abstract: A process of forming an integrated circuit containing elongated contacts which connect to three active areas and/or MOS gates, and elongated contacts which connect to two active areas and/or MOS gates and directly connect to a first level interconnect, using a litho-freeze-litho-etch process for a contact etch mask. A process of forming an integrated circuit containing elongated contacts which connect to three active areas and/or MOS gates, and elongated contacts which connect to two active areas and/or MOS gates and directly connect to a first level interconnect, using a litho-freeze-litho-etch process for a first level interconnect trench etch mask. A process of forming the integrated circuit using a litho-freeze-litho-etch process for a contact etch mask and a litho-freeze-litho-etch process for a first level interconnect trench etch mask.

Abstract: A process of forming an integrated circuit containing elongated contacts which connect to three active areas and/or MOS gates, and elongated contacts which connect to two active areas and/or MOS gates and directly connect to a first level interconnect, using a litho-freeze-litho-etch process for a contact etch mask. A process of forming an integrated circuit containing elongated contacts which connect to three active areas and/or MOS gates, and elongated contacts which connect to two active areas and/or MOS gates and directly connect to a first level interconnect, using a litho-freeze-litho-etch process for a first level interconnect trench etch mask. A process of forming the integrated circuit using a litho-freeze-litho-etch process for a contact etch mask and a litho-freeze-litho-etch process for a first level interconnect trench etch mask.

Abstract: A process of forming an integrated circuit containing elongated contacts which connect to three active areas and/or MOS gates, and elongated contacts which connect to two active areas and/or MOS gates and directly connect to a first level interconnect, using a litho-freeze-litho-etch process for a contact etch mask. A process of forming an integrated circuit containing elongated contacts which connect to three active areas and/or MOS gates, and elongated contacts which connect to two active areas and/or MOS gates and directly connect to a first level interconnect, using a litho-freeze-litho-etch process for a first level interconnect trench etch mask. A process of forming the integrated circuit using a litho-freeze-litho-etch process for a contact etch mask and a litho-freeze-litho-etch process for a first level interconnect trench etch mask.

Abstract: An integrated circuit containing elongated contacts, including elongated contacts which connect to at least three active areas and/or MOS gates, and including elongated contacts which connect to exactly two active areas and/or MOS gates and directly connect to a first level interconnect. A process of forming an integrated circuit containing elongated contacts, including elongated contacts which connect to at least three active areas and/or MOS gates, using exactly two contact photolithographic exposure operations, and including elongated contacts which connect to exactly two active areas and/or MOS gates and directly connect to a first level interconnect.

Abstract: A process of forming an integrated circuit containing elongated contacts which connect to three active areas and/or MOS gates, and elongated contacts which connect to two active areas and/or MOS gates and directly connect to a first level interconnect, using a litho-freeze-litho-etch process for a contact etch mask. A process of forming an integrated circuit containing elongated contacts which connect to three active areas and/or MOS gates, and elongated contacts which connect to two active areas and/or MOS gates and directly connect to a first level interconnect, using a litho-freeze-litho-etch process for a first level interconnect trench etch mask. A process of forming the integrated circuit using a litho-freeze-litho-etch process for a contact etch mask and a litho-freeze-litho-etch process for a first level interconnect trench etch mask.

Abstract: A method of aligning a new pattern to more than one previously defined pattern during the manufacture of an integrated circuit. A method of aligning a photolighography pattern reticle to a first previously defined pattern in a first direction and also aligning the photolithography pattern reticle to a second previously defined pattern in a second direction. A method of aligning a photolighography pattern reticle to two previously defined patterns in the same direction.

Abstract: An integrated circuit containing elongated contacts, including elongated contacts which connect to at least three active areas and/or MOS gates, and including elongated contacts which connect to exactly two active areas and/or MOS gates and directly connect to a first level interconnect. A process of forming an integrated circuit containing elongated contacts, including elongated contacts which connect to at least three active areas and/or MOS gates, using exactly two contact photolithographic exposure operations, and including elongated contacts which connect to exactly two active areas and/or MOS gates and directly connect to a first level interconnect.

Abstract: A process of forming an integrated circuit containing elongated contacts which connect to three active areas and/or MOS gates, and elongated contacts which connect to two active areas and/or MOS gates and directly connect to a first level interconnect, using a litho-freeze-litho-etch process for a contact etch mask. A process of forming an integrated circuit containing elongated contacts which connect to three active areas and/or MOS gates, and elongated contacts which connect to two active areas and/or MOS gates and directly connect to a first level interconnect, using a litho-freeze-litho-etch process for a first level interconnect trench etch mask. A process of forming the integrated circuit using a litho-freeze-litho-etch process for a contact etch mask and a litho-freeze-litho-etch process for a first level interconnect trench etch mask.

Abstract: A method of aligning a new pattern to more than one previously defined pattern during the manufacture of an integrated circuit. A method of aligning a photolighography pattern reticle to a first previously defined pattern in a first direction and also aligning the photolithography pattern reticle to a second previously defined pattern in a second direction. A method of aligning a photolighography pattern reticle to two previously defined patterns in the same direction.

Abstract: A method of aligning a new pattern to more than one previously defined pattern during the manufacture of an integrated circuit. A method of aligning a photolighography pattern reticle to a first previously defined pattern in a first direction and also aligning the photolithography pattern reticle to a second previously defined pattern in a second direction. A method of aligning a photolighography pattern reticle to two previously defined patterns in the same direction.