Abstract: There are provided a controller coupled to a semiconductor memory device and an operating method thereof. A controller having improved operation speed includes a command generation unit for generating commands to be performed by a semiconductor memory device, a command queue for storing the commands and providing at least one command among the stored commands to the semiconductor memory device, and a command removal unit for, if the semiconductor memory device fails in the performance of the at least one command output from the main command queue, removing the at least one command and related commands of the at least one command from the command queue.

Abstract: A controller includes a command generation unit suitable for generating a first read command for at least one page selected from said plurality of pages, an error correction block suitable for performing a first error correction operation to one or more code words stored in said at least one selected page in response to the first read command, and a command mirroring unit suitable for generating a mirrored command by mirroring the first read command.

Abstract: An operating method for controlling a semiconductor memory device according to an embodiment may include storing read commands in a command queue managed on first-in first-out basis; providing one of the read commands to the semiconductor memory device; determining whether the provided read command passes or fails based on read data, which is provided from the semiconductor memory device in response to the provided read command; and aborting remaining read commands in the command queue when the provided read command passes.

Abstract: A semiconductor system includes a semiconductor device suitable for receiving and performing a plurality of commands and a controller suitable for determining whether the semiconductor device completes an operation for each of the plurality of commands by performing one or more status reads for the semiconductor device whenever each of the plurality of commands is issued to the semiconductor device. The controller issues a first command among the plurality of commands to the semiconductor device, performs the one or more status reads for the semiconductor device to store a time taken to perform the first command as operation time information. The controller issues a second command among the plurality of commands to the semiconductor device, waits for a first wait time determined by the operation time information, and then performs the one or more status reads for the semiconductor device.

Abstract: An operating method for controlling a semiconductor memory device according to an embodiment may include storing read commands in a command queue managed on first-in first-out basis; providing one of the read commands to the semiconductor memory device; determining whether the provided read command passes or fails based on read data, which is provided from the semiconductor memory device in response to the provided read command; and aborting remaining read commands in the command queue when the provided read command passes.

Abstract: A semiconductor system includes a semiconductor device suitable for receiving and performing a plurality of commands and a controller suitable for determining whether the semiconductor device completes an operation for each of the plurality of commands by performing one or more status reads for the semiconductor device whenever each of the plurality of commands is issued to the semiconductor device. The controller issues a first command among the plurality of commands to the semiconductor device, performs the one or more status reads for the semiconductor device to store a time taken to perform the first command as operation time information. The controller issues a second command among the plurality of commands to the semiconductor device, waits for a first wait time determined by the operation time information, and then performs the one or more status reads for the semiconductor device.

Abstract: A cache programming method for a non-volatile memory device includes programming data for a current programming operation into a memory cell array, determining whether the current programming operation has been performed to a threshold point of program completion, and receiving a data for a next programming operation when the current programming operation has been performed to the threshold point of program completion.

Abstract: A data storage device and a method for operating the same are provided. In the data storage device and the method for operating the same, a predetermined number of memory chips are operated based on a usable power limitation when a power supply is supplied from a finite power supply source such as a battery, and as many memory chips as possible are operated in parallel. Accordingly, performance of the data storage device may be improved.

Abstract: A voltage generation circuit comprises a voltage generation control unit configured to output one of a first voltage level determination signal having a fixed data value and a second voltage level determination signal having a varying data value in response to a selection signal, and a voltage generation unit configured to generate a voltage having a single pulse form or a voltage having a pulse form whose rising edge portion rises in incremental voltage steps in response to the voltage level determination signal outputted from the voltage generation control unit.

Abstract: Methods for performing a fail test, block management, erase operations and program operations are used in a nonvolatile memory device having a block switch devoid of a fuse and a PMOS transistor. A method for performing a fail test in a nonvolatile memory device includes performing a fail test for a memory cell block; storing good block information in a block information store associated with the corresponding block when the memory cell block is a good block; and repeating the performing and storing steps for all memory cell blocks.

Abstract: A cache programming method for a non-volatile memory device includes programming data for a current programming operation into a memory cell array, determining whether the current programming operation has been performed to a threshold point of program completion, and receiving a data for a next programming operation when the current programming operation has been performed to the threshold point of program completion.

Abstract: Multi-level cell programming methods are provided. A method includes providing a page buffer including first and second registers connected to first and second memory cell blocks, respectively. A least significant bit (LSB) program of each memory cell is completed. Most significant bit (MSB) data is set in a first node of the first register. An MSB program is performed. When the MSB program is performed at a first verify voltage, first data at a first voltage level is set in the first node. When the MSB program is performed at a second verify voltage, second data at a second voltage level, opposite to the first voltage level, is set in the first node. When the MSB program is performed at a third verify voltage, the first data is set in the first node. The MSB program is repeated according to the first node data.

Abstract: A method of verifying data in a memory device having a page buffer for performing a program operation, a verifying operation and a read operation, includes: storing data to be programmed in a multi level cell of a first latching circuit in the page buffer; storing reference data set for the verifying operation in a second latching circuit; programming the data stored in the first latching circuit to the multi level cell; and verifying the programming of the data through a first node or a second node in the second latching circuit in accordance with a verifying voltage.

Abstract: A method of operating a nonvolatile memory device includes performing a reset operation for setting a level of a program voltage to a first level, performing a program operation and a verification operation on memory cells included in a first page of a first memory block while raising the program voltage from the first level, storing a level of the program voltage, supplied to the first page when memory cells programmed to have threshold voltages with at least a verification voltage are detected during the verification operation, as a second level, while raising the program voltage from the second level, performing the program operation and the verification operation on each of second to last pages of the first memory block, and after completing the program operation for the first memory block, performing the reset operation for setting the level of the program voltage to the first level.

Abstract: Multi-level cell programming methods are provided. A method includes providing a page buffer including first and second registers connected to first and second memory cell blocks, respectively. A least significant bit (LSB) program of each memory cell is completed. Most significant bit (MSB) data is set in a first node of the first register. An MSB program is performed. When the MSB program is performed at a first verify voltage, first data at a first voltage level is set in the first node. When the MSB program is performed at a second verify voltage, second data at a second voltage level, opposite to the first voltage level, is set in the first node. When the MSB program is performed at a third verify voltage, the first data is set in the first node. The MSB program is repeated according to the first node data.

Abstract: A page buffer includes a first register, a second register and a data I/O unit. The first register temporarily stores data to be programmed into cells included in a first memory cell block group, or reads and stores data of a corresponding memory cell. The second register temporarily stores data to be programmed into cells included in a second memory cell block group, or reads and stores data of a corresponding memory cell. The data I/O unit inputs specific data to the first register and the second register, or outputs data stored in the first register and the second register.

Abstract: A nonvolatile memory device includes a comparison unit configured to compare a reference voltage and a voltage of each of a plurality of nodes of a sample memory cell string, a state storage unit configured to store state information of each of memory cells depending on the corresponding comparison result of the comparison unit, and a high voltage generation unit configured to change a program start voltage depending on data stored in the state storage unit.

Abstract: A method of verifying data in a memory device having a page buffer for performing a program operation, a verifying operation and a read operation, includes: storing data to be programmed in a multi level cell of a first latching circuit in the page buffer; storing reference data set for the verifying operation in a second latching circuit; programming the data stored in the first latching circuit to the multi level cell; and verifying the programming of the data through a first node or a second node in the second latching circuit in accordance with a verifying voltage.

Abstract: A voltage generation circuit comprises a voltage generation control unit configured to output one of a first voltage level determination signal having a fixed data value and a second voltage level determination signal having a varying data value in response to a selection signal, and a voltage generation unit configured to generate a voltage having a single pulse form or a voltage having a pulse form whose rising edge portion rises in incremental voltage steps in response to the voltage level determination signal outputted from the voltage generation control unit.

Abstract: A nonvolatile memory device and its programming method includes a memory block having a number of memory cells, a page buffer unit coupled to the memory block and configured to temporarily store program data, to transmit the program data to the memory block, to perform a program operation for the program data, and to output the stored program in response to the memory block being treated as being a bad block, and a control unit configured to transmit the program data to the memory block, temporarily store the program data outputted from the page buffer unit, and transmit the stored program data to another page buffer unit coupled to another memory block.