Abstract: A memory device includes an erase operation controller for performing an erase operation on a memory block; an erase suspend count manager for managing an erase suspend count representing a number of times the erase operation is suspended until the erase operation on the memory block is completed; and a program parameter value determiner for determining a parameter value to be used for a program operation on the memory block, based on the erase suspend count.

Abstract: The present invention relates to a conjugate in which an immunoglobulin Fc region is linked to therapeutic enzymes through a non-peptide polymer linkage moiety, and more specifically, to a conjugate in which a non-peptide polymer linkage moiety is specifically linked to an immunoglobulin Fc, a method of preparing the same, and a composition comprising the same.

Abstract: Circuit designs and operating techniques for a storage device that includes, in one implementation, a memory controller configured to control a memory device including a plurality of memory blocks, each including a plurality of memory cells. The memory controller may include a memory device interface configured to perform data communication with the memory device, and a soft program controller communicatively coupled to the memory device interface and configured to count a number of iterations that an erase operation on an erase target memory block, among the plurality of memory blocks, has been suspended until the erase operation is completed, and to perform a soft program operation on the erase target memory block after the erase operation has been completed, based on the number of iterations that the erase operation on the erase target memory block has been suspended.

Abstract: A memory system may include a memory cell array including a plurality of memory blocks; a peripheral circuit configured to apply a check voltage for acquiring check data to a target memory block and apply program voltages to the target memory block in a pre-program operation for the target memory block; and a controller configured to control the peripheral circuit, determine status information on the target memory block based on the check data, and variably apply a program start voltage to the target memory block based on the status information in the pre-program operation.

Abstract: A memory system includes a memory cell array including a plurality of memory cells; a peripheral circuit configured to apply a read voltage to a selected word line coupled to a selected memory cell among the memory cells, and apply a pass voltage to unselected word lines coupled to unselected memory cells other than the selected memory cell among the memory cells, during a read operation; and a controller configured to control the peripheral circuit, and apply a variable voltage level of the pass voltage based on status information of a target memory block which is the target of the read operation.

Abstract: The present invention relates to insulin and/or an insulin analogue conjugate, and a use thereof, wherein the insulin and/or insulin analogue have improved in vivo durability and stability by linking the same with an Fc region of immunoglobulin. The insulin and/or an insulin analogue conjugate of the present invention show an in vivo activity similar to that of insulin. In addition, the insulin and/or insulin analogue conjugate of the present invention are long-acting formulations of insulin and/or the analogue thereof, in which serum half-life is remarkably increased, and therefore, the present invention provides remarkable insulin and/or an insulin analogue conjugate, which do not induce hypoglycemia, a drawback of insulin treatment.

Abstract: The present invention relates to a novel glucagon derivative peptide, and a composition for preventing or treating hypoglycemia containing the novel glucagon derivative peptide as an active ingredient. The glucagon derivative according to the present invention has improved physical properties due to the change in isoelectric point (pI) while being capable of maintaining an activity on glucagon receptors, and thus can improve patient compliance when used as a hypoglycemic agent, and is also suitable for administration in combination with other anti-obesity agents. Accordingly, the glucagon derivative according to the present invention can be effectively used for the prevention and treatment of hypoglycemia and obesity.

Abstract: A coil electronic component includes a body and external terminals. The body includes a winding coil part and a pillar-shaped core part inserted inside of the winding coil part and formed of a magnetic metal. The external terminals are connected to the winding coil part and disposed on an external surface of the body. The body contains the magnetic metal and a resin, and the pillar-shaped core part has magnetic permeability higher than that of a portion of the body disposed outside of the winding coil part.

Abstract: A memory device includes an erase operation controller for performing an erase operation on a memory block; an erase suspend count manager for managing an erase suspend count representing a number of times the erase operation is suspended until the erase operation on the memory block is completed; and a program parameter value determiner for determining a parameter value to be used for a program operation on the memory block, based on the erase suspend count.

Abstract: A memory device includes a memory cell array including a plurality of memory blocks; a peripheral circuit configured to sequentially perform a channel initialization operation and a read operation on a memory block selected from among the plurality of memory blocks; and control logic configured to control the peripheral circuit to perform the channel initialization operation and the read operation, wherein the control logic sets a time during which the channel initialization operation is to be performed as channel initialization period depending on a potential level of supply voltage, the channel initialization operation being performed to remove hot holes in a channel of the selected memory block.

Abstract: An insulin conjugate having improved in vivo duration and stability is provided. The conjugate is prepared by covalently linking insulin with an immunoglobulin Fc region via a non-peptidyl polymer, a long-acting formulation comprising the same, and a preparation method thereof. The insulin conjugate of the present invention maintains in vivo activity of the peptide at a relatively high level and remarkably increases the serum half-life thereof, thereby greatly improving drug compliance upon insulin treatment.

Abstract: Provided is a conjugate in which an immunoglobulin Fc region is linked to an iduronate-2-sulfatase enzyme through a non-peptide polymer linker moiety. Further, provided are a conjugate, a method for preparing the same, and a composition including the same in which a non-peptide polymer linker moiety is specifically linked to an immunoglobulin Fc.

Abstract: The present disclosure relates to an electronic device. A storage device having improved reliability may include a memory device performing a program operation of storing data in selected memory cells, among a plurality of memory cells included in a memory block, and a memory controller controlling the memory device to perform a retention control operation of applying a retention control voltage to at least one source line coupled to a plurality of memory cell strings included in the memory block for a predetermined time duration when the program operation is completed.

Abstract: A method for preparing a conjugate by linking a physiologically active polypeptide, a non-peptidyl polymer linker, and an immunoglobulin constant region via a covalent bond are disclosed. The method enables an efficient preparation of a physiologically active polypeptide conjugate, in which a salt is used in a coupling reaction to improve the problem of low production yield during preparation of the physiologically active polypeptide conjugate.

Abstract: A roll-to-roll printing process for large scale manufacturing of nanosensor systems for sensing pathophysiological signals is disclosed. The roll-to-roll manufacturing process may include three processes to improve the throughput and to reduce the cost in manufacturing: fabrication of textile based nanosensors, printing conductive tracks, and integration of electronics. The wireless nanosensor systems can be used in different monitoring applications. The fabric sheet printed and integrated with the customized components can be used in a variety of different applications. The electronics in the nanosensor systems connect to remote severs through adhoc networks or cloud networks with standard communication protocols or non-standard customized protocols for remote health monitoring.

Abstract: An insulin analog with an improved in vitro effect compared with native insulin, a pharmaceutical composition for treating diabetes containing the insulin analog as an active ingredient, and a method for treating diabetes using the insulin analog or the pharmaceutical composition are described. A nucleic acid encoding the insulin analog, an expression vector including the nucleic acid, a transformant introduced with the expression vector, and a method of producing the insulin analog from the transformant are also described.

Abstract: The present invention relates to a novel peptide of a glucagon derivative and a composition for preventing or treating obesity comprising the peptide as an active ingredient. The glucagon derivative according to the present invention shows a more excellent activating effect with regard to both glucagon-like peptide-1 receptors and glucagon receptors compared to native glucagon, and thus can be widely used as an effective agent for treating obesity.

Abstract: There are provided a memory controller and a memory system having the same. The memory controller includes: a central processing unit configured to output a read command for checking an erase state of a selected storage region in response to a program request from a host, determine the number of dummy pages according to the erase state, and output a program command according to the number of dummy pages; and a memory interface configured to, when user data corresponding to the program request is output to the selected storage region, selectively generate dummy data corresponding to the number of dummy pages, and output the dummy data with the user data.

Abstract: Circuit designs and operating techniques for a storage device that includes, in one implementation, a memory controller configured to control a memory device including a plurality of memory blocks, each including a plurality of memory cells. The memory controller may include a memory device interface configured to perform data communication with the memory device, and a soft program controller communicatively coupled to the memory device interface and configured to count a number of times that an erase operation on an erase target memory block, among the plurality of memory blocks, has been suspended until the erase operation is completed, and to perform a soft program operation on the erase target memory block after the erase operation has been completed, based on the number of iterations that the erase operation on the erase target memory block has been suspended.

Abstract: The technology disclosed in this patent document can be implemented in embodiments to provide a memory controller configured to control a memory device and a method of operating the memory controller and the memory device. The memory controller may control a memory device including a plurality of pages, and may include a command analysis unit configured to generate command information indicating a type of read command for a page selected from among the plurality of pages, and an initialization time decision unit configured to decide on a channel initialization time for initializing channels of a plurality of memory cells included in the selected page based on the command information.