Abstract: Disclosed is a timing circuit which produces control signals by which a data interfacing section can simultaneously implement input and output operations of a video data from a frame memory and to an address electrode driving section, respectively. A first pulse signal whose pulse duration corresponds to a whole horizontal line time, a second pulse signal which is identical to a delayed first pulse signal by one horizontal line time and a third pulse signal whose pulse duration is the one horizontal line time longer than that of the first pulse signal are produced by using a system clock signal of 2 MHz. During the pulse duration of the third pulse signal, a first clock signal which contains pulse signals whose numbers are one number larger than the numbers of whole horizontal lines (480) by using a system clock signal of 25 MHz. The first clock signal is provided to the data interfacing section to control the input and output operations thereof.

Abstract: An apparatus for L pixel data corresponding to 1 line input from a memory section to an upper and a lower address electrode driving sections, respectively in response to a control signal supplied from a timing control section. The data interfacing apparatus includes upper and lower data interfacing sections, and an input/output control section. The upper and the lower data interfacing sections includes a couple of temporality storing sections including a storing area for temporarily storing L/2 pixel data, an input selecting section for inputting 3N pixel data into the storing area over M (where M is a least integer which is greater than quotient of L divided by 3N) times in response to M input selecting control signals which are sequentially generated, and an output selecting section for outputting the L/2 pixel data stored in the storing area by P units over Q {=(L/2)/P} times in response to Q output selecting control signals which are sequentially generated, respectively.

Abstract: A data processing apparatus of an alternating current type plasma display panel system is disclosed. A plasma panel is divided into four subpanels by dividing vertically and horizontally, and 4 data interfacing sections take charge of driving the 4 subpanels, respectively. Numbers of upper and lower address electrodes are P. Each of the four data interfacing sections repeatedly receives N bits red-green-blue (RGB) data S times from a frame memory and, after storing a horizontal line RGB data, transfers D bits RGB data a time into 4 driving IC sections for driving address electrodes in a suitable order for data processing. Each of two driving IC sections for upper right and lower right subpanels takes charge of driving R address electrodes, and each of two driving IC sections for upper left and lower left subpanels takes charge of driving P-R address electrodes, where the number R can be decided by an equation, R=N.times.

Abstract: A method and an apparatus for control a timing in a flat panel display system are disclosed. In an alternating current plasma display system for respectively driving a plurality of subfields at every field in three steps such as a) entering and for eliminating a whole pixel for a first predetermined time, b) entering data for a second predetermined time and c) maintaining a discharge at every subfield for times which are different from one another, a first clock generator generates a first clock signal having a high frequency. A second clock generator generates a second clock signal having a low frequency. A first counter counts the second clock signal in response to a vertical synchronizing signal, and generates both a first pulse signal which sets the first and second predetermined times respectively in steps a) and b) in the respective subfield sections and a second pulse signal which sets times in step c) in the respective subfield sections which are different from one another.