Patents by Inventor Se-Young Yang
Se-Young Yang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20150303149Abstract: In some embodiments, a semiconductor device package assembly may include a first substrate. The first substrate may include a first set of electrical conductors which electrically connect the assembly. In some embodiments, the assembly may include at least one electrical conductor coupled to the first substrate such that at least one of the electrical conductors exposes through a perimeter surface of the semiconductor device package assembly. In some embodiments, the assembly may include a first die electrically connected to a second surface of the first substrate using a second set of electrical conductors. The assembly may include an electronic memory module coupled to the first die. In some embodiments, the assembly may include a shield applied to an upper surface of the assembly and electrically coupled to at least one of the exposed electrical conductors. The shield may inhibit, during use, electromagnetic interference.Type: ApplicationFiled: July 15, 2014Publication date: October 22, 2015Inventors: Jun Zhai, Mengzhi Pang, Se Young Yang, Leland W. Lew
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Publication number: 20150255424Abstract: A microelectronic package includes a substrate having a first surface. A microelectronic element overlies the first surface. Electrically conductive elements are exposed at the first surface of the substrate, at least some of which are electrically connected to the microelectronic element. The package includes wire bonds having bases bonded to respective ones of the conductive elements and ends remote from the substrate and remote from the bases. The ends of the wire bonds are defined on tips of the wire bonds, and the wire bonds define respective first diameters between the bases and the tips thereof. The tips have at least one dimension that is smaller than the respective first diameters of the wire bonds. A dielectric encapsulation layer covers portions of the wire bonds, and unencapsulated portions of the wire bonds are defined by portions of the wire bonds, including the ends, are uncovered by the encapsulation layer.Type: ApplicationFiled: May 21, 2015Publication date: September 10, 2015Inventors: Ellis Chau, Reynaldo Co, Roseann Alatorre, Philip Damberg, Wei-Shun Wang, Se Young Yang
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Patent number: 9105483Abstract: A microelectronic package can include wire bonds having bases bonded to respective ones of conductive elements exposed at a surface of a substrate. The wire bonds may have exterior edge surfaces disposed at an angle between 25° and 90° relative to the bases, and ends remote, e.g., opposite, from the bases, and remote from the ends which are connected to the bases. A dielectric encapsulation layer extends from the substrate and covers portions of the wire bonds such that covered portions of the wire bonds are separated from one another by the encapsulation layer, wherein unencapsulated portions of the wire bonds are defined by portions of the wire bonds that are uncovered by the encapsulation layer, the unencapsulated portions including the ends of the wire bonds.Type: GrantFiled: February 24, 2012Date of Patent: August 11, 2015Assignee: Invensas CorporationInventors: Ellis Chau, Reynaldo Co, Roseann Alatorre, Philip Damberg, Wei-Shun Wang, Se Young Yang
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Patent number: 9041227Abstract: A microelectronic package includes a substrate having a first surface. A microelectronic element overlies the first surface. Electrically conductive elements are exposed at the first surface of the substrate, at least some of which are electrically connected to the microelectronic element. The package includes wire bonds having bases bonded to respective ones of the conductive elements and ends remote from the substrate and remote from the bases. The ends of the wire bonds are defined on tips of the wire bonds, and the wire bonds define respective first diameters between the bases and the tips thereof. The tips have at least one dimension that is smaller than the respective first diameters of the wire bonds. A dielectric encapsulation layer covers portions of the wire bonds, and unencapsulated portions of the wire bonds are defined by portions of the wire bonds, including the ends, are uncovered by the encapsulation layer.Type: GrantFiled: March 12, 2013Date of Patent: May 26, 2015Assignee: Invensas CorporationInventors: Ellis Chau, Reynaldo Co, Roseann Alatorre, Philip Damberg, Wei-Shun Wang, Se Young Yang
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Patent number: 8978247Abstract: A method for forming an interconnection element having metalized structures includes forming metalized structures in an in-process unit that has a support material layer with first and second spaced-apart surfaces defining a thickness therebetween, a handling structure, and an insulating layer separating at least portions of the first surface of the support material layer from at least portions of the handling structure. The metalized structures are formed extending through the thickness of the support material layer. The method also includes etching at least a portion of the insulating layer to remove the handling structure from the in-process unit and further processing the in-process unit to form the interconnection element.Type: GrantFiled: May 22, 2012Date of Patent: March 17, 2015Assignee: Invensas CorporationInventors: Se Young Yang, Cyprian Emeka Uzoh, Michael Huynh, Rajesh Katkar
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Publication number: 20150014688Abstract: A method of attaching a microelectronic element to a substrate can include aligning the substrate with a microelectronic element, the microelectronic element having a plurality of spaced-apart electrically conductive bumps each including a bond metal, and reflowing the bumps. The bumps can be exposed at a front surface of the microelectronic element. The substrate can have a plurality of spaced-apart recesses extending from a first surface thereof. The recesses can each have at least a portion of one or more inner surfaces that are non-wettable by the bond metal of which the bumps are formed. The reflowing of the bumps can be performed so that at least some of the bond metal of each bump liquefies and flows at least partially into one of the recesses and solidifies therein such that the reflowed bond material in at least some of the recesses mechanically engages the substrate.Type: ApplicationFiled: September 29, 2014Publication date: January 15, 2015Applicant: Invensas CorporationInventors: Charles G. Woychik, Se Young Yang, Pezhman Monadgemi, Terrence Caskey
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Patent number: 8846447Abstract: A method of attaching a microelectronic element to a substrate can include aligning the substrate with a microelectronic element, the microelectronic element having a plurality of spaced-apart electrically conductive bumps each including a bond metal, and reflowing the bumps. The bumps can be exposed at a front surface of the microelectronic element. The substrate can have a plurality of spaced-apart recesses extending from a first surface thereof. The recesses can each have at least a portion of one or more inner surfaces that are non-wettable by the bond metal of which the bumps are formed. The reflowing of the bumps can be performed so that at least some of the bond metal of each bump liquefies and flows at least partially into one of the recesses and solidifies therein such that the reflowed bond material in at least some of the recesses mechanically engages the substrate.Type: GrantFiled: August 23, 2012Date of Patent: September 30, 2014Assignee: Invensas CorporationInventors: Charles G. Woychik, Se Young Yang, Pezhman Monadgemi, Terrence Caskey, Cyprian Emeka Uzoh
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Patent number: 8836136Abstract: A microelectronic package can include wire bonds having bases bonded to respective conductive elements on a substrate and ends opposite the bases. A dielectric encapsulation layer extending from the substrate covers portions of the wire bonds such that covered portions of the wire bonds are separated from one another by the encapsulation layer, wherein unencapsulated portions of the wire bonds are defined by portions of the wire bonds which are uncovered by the encapsulation layer. Unencapsulated portions can be disposed at positions in a pattern having a minimum pitch which is greater than a first minimum pitch between bases of adjacent wire bonds.Type: GrantFiled: February 24, 2012Date of Patent: September 16, 2014Assignee: Invensas CorporationInventors: Ellis Chau, Reynaldo Co, Roseann Alatorre, Philip Damberg, Wei-Shun Wang, Se Young Yang, Zhijun Zhao
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Publication number: 20140054763Abstract: A method of attaching a microelectronic element to a substrate can include aligning the substrate with a microelectronic element, the microelectronic element having a plurality of spaced-apart electrically conductive bumps each including a bond metal, and reflowing the bumps. The bumps can be exposed at a front surface of the microelectronic element. The substrate can have a plurality of spaced-apart recesses extending from a first surface thereof. The recesses can each have at least a portion of one or more inner surfaces that are non-wettable by the bond metal of which the bumps are formed. The reflowing of the bumps can be performed so that at least some of the bond metal of each bump liquefies and flows at least partially into one of the recesses and solidifies therein such that the reflowed bond material in at least some of the recesses mechanically engages the substrate.Type: ApplicationFiled: August 23, 2012Publication date: February 27, 2014Applicant: Invensas CorporationInventors: Charles G. Woychik, Se Young Yang, Pezhman Monadgemi, Terrence Caskey, Cyprian Emeka Uzoh
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Publication number: 20130328219Abstract: A structure includes a substrate having a first region and a second region, the substrate also having a first surface and a second surface. Electrically conductive elements are exposed at the first surface within the second region. Wire bonds have bases bonded to respective ones of the conductive elements and ends remote from the substrate and remote from the bases. At least one of the wire bonds has a shape such that the wire bond defines an axis between the free end and the base thereof and such that the wire bond defines a plane. A bent portion of the at least one wire bond extends away from the axis within the plane. A dielectric encapsulation layer covers portions of the wire bonds such that unencapsulated portions, including the ends, of the wire bonds are defined by portions of the wire bonds that are uncovered by the encapsulation layer.Type: ApplicationFiled: August 14, 2013Publication date: December 12, 2013Applicant: INVENSAS CORPORATIONInventors: Ellis Chau, Reynaldo Co, Roseann Alatorre, Philip Damberg, Wei-Shun Wang, Se Young Yang
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Publication number: 20130313012Abstract: A method for forming an interconnection element having metalized structures includes forming metalized structures in an in-process unit that has a support material layer with first and second spaced-apart surfaces defining a thickness therebetween, a handling structure, and an insulating layer separating at least portions of the first surface of the support material layer from at least portions of the handling structure. The metalized structures are formed extending through the thickness of the support material layer. The method also includes etching at least a portion of the insulating layer to remove the handling structure from the in-process unit and further processing the in-process unit to form the interconnection element.Type: ApplicationFiled: May 22, 2012Publication date: November 28, 2013Applicant: INVENSAS CORPORATIONInventors: Se Young Yang, Cyprian Emeka Uzoh, Michael Huynh, Rajesh Katkar
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Publication number: 20130171738Abstract: A chemical sensor that works while being submerged in a highly conductive medium is described. The chemical sensor includes hydrophobic structures that are distributed on conductive electrodes and are separated by small air cavities while submerged in the conductive medium. The hydrophobic structures are arranged such that their hydrophobicity varies in response to exposure to a target analyte. The change in the level of hydrophobicity results in permeation of the conductive liquid on to the conductive electrodes, thereby reducing the resistance levels between the conductive electrodes. The sensor indicates presence of the target analyte in response to detection of a change in resistance between at least two of the conductive electrodes.Type: ApplicationFiled: June 17, 2011Publication date: July 4, 2013Applicant: MASSACHUSETTS INSTITUTE OF TECHNOLOGYInventors: Hyungryul Johnny Choi, Ayse Asatekin Alexiou, Se Young Yang, Christy D. Petruczok, Karen K. Gleason, Nicholas M. Patrikalakis, George Barbastathis
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Publication number: 20130093088Abstract: A microelectronic package can include wire bonds having bases bonded to respective conductive elements on a substrate and ends opposite the bases. A dielectric encapsulation layer extending from the substrate covers portions of the wire bonds such that covered portions of the wire bonds are separated from one another by the encapsulation layer, wherein unencapsulated portions of the wire bonds are defined by portions of the wire bonds which are uncovered by the encapsulation layer. Unencapsulated portions can be disposed at positions in a pattern having a minimum pitch which is greater than a first minimum pitch between bases of adjacent wire bonds.Type: ApplicationFiled: February 24, 2012Publication date: April 18, 2013Applicant: INVENSAS CORPORATIONInventors: Ellis Chau, Reynaldo Co, Roseann Alatorre, Philip Damberg, Wei-Shun Wang, Se Young Yang, Zhijun Zhao
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Publication number: 20130095610Abstract: A microelectronic package can include wire bonds having bases bonded to respective ones of conductive elements exposed at a surface of a substrate. The wire bonds may have exterior edge surfaces disposed at an angle between 25° and 92° relative to the bases, and ends remote, e.g., opposite, from the bases, and remote from the ends which are connected to the bases. A dielectric encapsulation layer extends from the substrate and covers portions of the wire bonds such that covered portions of the wire bonds are separated from one another by the encapsulation layer, wherein unencapsulated portions of the wire bonds are defined by portions of the wire bonds that are uncovered by the encapsulation layer, the unencapsulated portions including the ends of the wire bonds.Type: ApplicationFiled: February 24, 2012Publication date: April 18, 2013Applicant: INVENSAS CORPORATIONInventors: Ellis Chau, Reynaldo Co, Roseann Alatorre, Philip Damberg, Wei-Shun Wang, Se Young Yang
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Publication number: 20130093087Abstract: A microelectronic package can include wire bonds having bases bonded to respective ones of conductive elements exposed at a surface of a substrate. The wire bonds may have exterior edge surfaces disposed at an angle between 25° and 90° relative to the bases, and ends remote, e.g., opposite, from the bases, and remote from the ends which are connected to the bases. A dielectric encapsulation layer extends from the substrate and covers portions of the wire bonds such that covered portions of the wire bonds are separated from one another by the encapsulation layer, wherein unencapsulated portions of the wire bonds are defined by portions of the wire bonds that are uncovered by the encapsulation layer, the unencapsulated portions including the ends of the wire bonds.Type: ApplicationFiled: February 24, 2012Publication date: April 18, 2013Applicant: INVENSAS CORPORATIONInventors: Ellis Chau, Reynaldo Co, Roseann Alatorre, Philip Damberg, Wei-Shun Wang, Se Young Yang
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Patent number: 8404520Abstract: A microelectronic package can include wire bonds having bases bonded to respective ones of conductive elements exposed at a surface of a substrate. The wire bonds may have exterior edge surfaces disposed at an angle between 25° and 92° relative to the bases, and ends remote, e.g., opposite, from the bases, and remote from the ends which are connected to the bases. A dielectric encapsulation layer extends from the substrate and covers portions of the wire bonds such that covered portions of the wire bonds are separated from one another by the encapsulation layer, wherein unencapsulated portions of the wire bonds are defined by portions of the wire bonds that are uncovered by the encapsulation layer, the unencapsulated portions including the ends of the wire bonds.Type: GrantFiled: February 24, 2012Date of Patent: March 26, 2013Assignee: Invensas CorporationInventors: Ellis Chau, Reynaldo Co, Roseann Alatorre, Philip Damberg, Wei-Shun Wang, Se Young Yang
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Patent number: 7884487Abstract: Provided are a rotation joint capable of compensating for a mismatch due to thermal expansion and a semiconductor device having the same. The rotation joint can include a support member and a first contact member coupled to a first portion of the support member such that a surface of the first contact member is moveable relative to a surface of the support member adjacent to the first contact member. The first contact member can include solder material.Type: GrantFiled: November 19, 2007Date of Patent: February 8, 2011Assignee: Samsung Electronics Co., Ltd.Inventors: Se-Young Yang, Wang-Ju Lee
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Patent number: 7777308Abstract: Integrated circuit packages include an integrated circuit mounting substrate having a hole that defines an inner wall of the integrated circuit mounting substrate. An integrated circuit is provided in the hole. A sinuous lead frame extends from the integrated circuit and is connected to the inner wall. The sinuous lead frame extends back and forth along a given direction, and may include a U- and/or V-shape, and round and/or jagged portions. Related packaging methods are also disclosed.Type: GrantFiled: October 28, 2008Date of Patent: August 17, 2010Assignee: Samsung Electronics Co., Ltd.Inventors: Se-Young Yang, Sun-Won Kang, Yeo-Hoon Yoon
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Patent number: 7692314Abstract: Provided is a wafer level chip scale package that reduces the parasitic capacitance generated between ball pads and the solder balls, and enhances the joint reliability between the ball pads and the solder balls. The wafer level chip scale package provides a conductive pattern in each ball pad section, on which a solder ball is mounted, so as to have a spiral or mesh shape, provides a space defined by the conductive pattern such that a first dielectric layer under the conductive pattern is exposed, and provides the solder ball on a top surface of each ball pad section such that part of the solder ball is inserted into the space defined by the conductive pattern. When viewed from the top, the dielectric layer is exposed from each ball pad section by an area of about 50% or less.Type: GrantFiled: August 27, 2007Date of Patent: April 6, 2010Assignee: Samsung Electronics Co., Ltd.Inventors: Se-Young Yang, Wang-Ju Lee
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Publication number: 20100081236Abstract: A method of manufacturing a semiconductor device includes forming printed circuit board (PCB) having an embedded interposer. A semiconductor chip or a semiconductor package is mounted onto the embedded interposer using a conductive adhesive agent. The embedded interposer has substantially the same coefficient of thermal expansion (CTE) as the semiconductor chip. The embedded interposer is formed using a semiconductor wafer.Type: ApplicationFiled: September 30, 2009Publication date: April 1, 2010Applicant: Samsung Electronics Co., LtdInventors: Se-Young Yang, Kyu-Jin Lee, Pyoung-Wan Kim, Keum-Hee Ma, Chul-Yong Jang