Abstract: The present invention provides methods and compositions based on a non-naturally occurring nucleic acid construct encoding a fusion protein for quantitating levels of secretion in a single cell which may comprise a protein sequence which may comprise a cytoplasmic domain, a transmembrane domain and a vesicular domain, wherein the vesicular domain may comprise a protein tag sequence, wherein upon expression of the fusion protein by a cell, the fusion protein localizes to the membrane of a secretory vesicle such that the protein tag localizes to the lumen of the secretory vesicle, and wherein the protein tag binds to a cell-impermeable marker; whereby upon secretion of the contents of the secretory vesicle, the protein tag is exposed to the cell-impermeable marker, the fusion protein is recycled back into the cell, and the single cell becomes labeled with the marker relative to the amount of secretion.

Abstract: In some implementations, a probe tip assembly includes a driver printed circuit board assembly (PCBA) and a probe tip subassembly. The probe tip subassembly includes a plurality of probe tips, wherein a probe tip, of the plurality of probe tips, extends beyond an end of the PCBA, and the PCBA and the probe tip are configured to transmit an electric signal to test an optical component. The probe tip may include a material comprising at least one of copper (Cu), a beryllium copper (BeCu) alloy, tungsten (W), Paliney, Neyoro, and/or another conductive material.

Abstract: A driver circuit may include an optical emitter, a capacitive element, and an inductive element. The driver circuit may include a first switch that, in a closed state, is to cause charging of the inductive element, and when transitioning from the closed state to an open state is to cause discharging of the inductive element to charge the capacitive element. The driver circuit may include a second switch that in a closed state is to cause discharging of the capacitive element to provide an electrical pulse to the optical emitter. The driver circuit may include a signal generator configured to generate a first signal for controlling the open state and the closed state of the first switch, and a pulse shortening element configured to shorten a pulse width of the first signal to generate a second signal for controlling the open state and the closed state of the second switch.

Abstract: In some implementations, a driver circuit may include a source to provide an electrical input and an array of optical emitters arranged in one or more rows and one or more columns. The array of optical emitters may include an optical emitter associated with a row of the one or more rows and a column of the one or more columns. The driver circuit may include a first switch having an open state and a closed state and a capacitive element connected to the row. The first switch in the closed state may cause charging of the capacitive element. The driver circuit may include a second switch having an open state and a closed state. The second switch in the closed state may select the column, and may cause discharging of the capacitive element through the row and the column to provide an electrical pulse to the optical emitter.

Abstract: In some implementations, a probe tip assembly includes a driver printed circuit board assembly (PCBA) and a probe tip subassembly. The probe tip subassembly includes a plurality of probe tips, wherein a probe tip, of the plurality of probe tips, extends beyond an end of the PCBA, and the PCBA and the probe tip are configured to transmit an electric signal to test an optical component. The probe tip may include a material comprising at least one of copper (Cu), a beryllium copper (BeCu) alloy, tungsten (W), Paliney, Neyoro, and/or another conductive material.

Abstract: According to one or more embodiments of the present invention a computer-implemented method for fabricating a chip includes generating, using an aerial image generation system, a set of aerial images for a chip layout, the set of aerial images including an aerial image corresponding to each region from the chip layout. The method further includes automatically determining, using an artificial neural network, a feature vector for each aerial image from the set of aerial images. The method further includes clustering the aerial images using their corresponding feature vectors. The method further includes selecting, as test samples, a predetermined number of aerial images from each cluster. The method further includes performing a pattern coverage inspection of the chip layout using the aerial images that are selected as test samples.

Abstract: A wafer testing system may comprise a chuck, a wafer carrier, a cathode plate, and a probe card. The chuck may be configured to hold the wafer carrier. The wafer carrier may be configured to hold a wafer on a surface of the wafer carrier, wherein the surface of the wafer carrier comprises one or more contact features protruding from the surface of the wafer carrier. The cathode plate may be configured to provide an electrical connection between the wafer carrier and the probe card, wherein a portion of a surface of the cathode plate is configured to be disposed on the one or more contact features of the wafer carrier. The probe card may be configured to test, using one or more probes associated with the probe card, the wafer when the wafer is on the surface of the wafer carrier.

Abstract: A wafer testing system may comprise a chuck, a wafer carrier, a cathode plate, and a probe card. The chuck may be configured to hold the wafer carrier. The wafer carrier may be configured to hold a wafer on a surface of the wafer carrier, wherein the surface of the wafer carrier comprises one or more contact features protruding from the surface of the wafer carrier. The cathode plate may be configured to provide an electrical connection between the wafer carrier and the probe card, wherein a portion of a surface of the cathode plate is configured to be disposed on the one or more contact features of the wafer carrier. The probe card may be configured to test, using one or more probes associated with the probe card, the wafer when the wafer is on the surface of the wafer carrier.

Abstract: The present invention provides methods and compositions based on a non-naturally occurring nucleic acid construct encoding a fusion protein for quantitating levels of secretion in a single cell which may comprise a protein sequence which may comprise a cytoplasmic domain, a transmembrane domain and a vesicular domain, wherein the vesicular domain may comprise a protein tag sequence, wherein upon expression of the fusion protein by a cell, the fusion protein localizes to the membrane of a secretory vesicle such that the protein tag localizes to the lumen of the secretory vesicle, and wherein the protein tag binds to a cell-impermeable marker, whereby upon secretion of the contents of the secretory vesicle, the protein tag is exposed to the cell-impermeable marker, the fusion protein is recycled back into the cell, and the single cell becomes labeled with the marker relative to the amount of secretion.

Abstract: According to one or more embodiments of the present invention a computer-implemented method for fabricating a chip includes generating, using an aerial image generation system, a set of aerial images for a chip layout, the set of aerial images including an aerial image corresponding to each region from the chip layout. The method further includes automatically determining, using an artificial neural network, a feature vector for each aerial image from the set of aerial images. The method further includes clustering the aerial images using their corresponding feature vectors. The method further includes selecting, as test samples, a predetermined number of aerial images from each cluster. The method further includes performing a pattern coverage inspection of the chip layout using the aerial images that are selected as test samples.

Abstract: A technique relates to a circuit. At least one 4 transistor (4T) static random access memory (SRAM) bitcell is included. Each of the 4T SRAM bitcells includes a first PFET, a first NFET, a second PFET, and a second NFET, the first PFET and the first NFET being coupled to form a first output node, and the second PFET and the second NFET being coupled to form a second output node. A pulldown circuit is coupled to the first NFET, the pulldown circuit operable to pull down a voltage at the first output node. A feedback circuit is operable to monitor the first output node, the feedback circuit operable to control the pulldown circuit.

Abstract: A wafer element with a tight-pitch formation is provided. The wafer element includes an alternating material hard mask comprising a repeating array of abutting first, second and third vertical elements. The first, second and third vertical elements are formed of first, second and third materials, respectively. The first material is selectively etchable with respect to the second and third materials, the second material is selectively etchable with respect to the first and third materials and the third material is selectively etchable with respect to the first and second materials.

Abstract: A method for generating physical design layout patterns includes selecting as training data a set of physical design layout patterns of patterned structures. The method also includes training, utilizing physical design layout patterns containing hotspots, a first neural network model configured to generate synthetic physical design layout patterns, and training, utilizing physical design layout patterns that do and do not contain hotspots, a second neural network model configured to classify whether physical design layout patterns contain hotspots. The method further includes generating synthetic physical design layout patterns containing hotspots by utilizing the trained first neural network model to generate synthetic physical design layout patterns and utilizing the trained second neural network model to select the synthetic physical design layout patterns containing hotspots.

Abstract: Ultra dense and stable 4T SRAM designs are provided. In one aspect, a 4T SRAM bitcell includes: two NFETs cross-coupled with two PFETs, wherein the NFETs are both connected directly to a word line, wherein a first one of the PFETs is connected to a first bit line via a first one of the NFETs and a second one of the PFETs is connected to a second bit line via a second one of the NFETs, and wherein the PFETs are each separately connected to ground. An SRAM device including the present 4T SRAM bitcell as well as a method of operating the SRAM device are also provided.

Abstract: The present invention provides nucleic acid constructs that encode fusion peptides comprising a bioluminescent protein and a precursor of a secreted peptide or protein expressed at the cell surface and high throughput screening assays using same.

Abstract: Ultra dense and stable 4T SRAM designs are provided. In one aspect, a 4T SRAM bitcell includes: two NFETs cross-coupled with two PFETs, wherein the NFETs are both connected directly to a word line, wherein a first one of the PFETs is connected to a first bit line via a first one of the NFETs and a second one of the PFETs is connected to a second bit line via a second one of the NFETs, and wherein the PFETs are each separately connected to ground. An SRAM device including the present 4T SRAM bitcell as well as a method of operating the SRAM device are also provided.

Abstract: The present invention provides nucleic acid constructs that encode fusion peptides comprising a bioluminescent protein and a precursor of a secreted peptide or protein expressed at the cell surface and high throughput screening assays using same.

Abstract: The present invention provides nucleic acid constructs that encode fusion peptides comprising a bioluminescent protein and a precursor of a secreted peptide or protein expressed at the cell surface and high throughput screening assays using same.

Abstract: The present invention provides nucleic acid constructs that encode fusion peptides comprising a bioluminescent protein and a precursor of a secreted peptide or protein expressed at the cell surface and high throughput screening assays using same.

Abstract: Inspection methods. A method includes adhering an optical blocking layer directly onto and in direct mechanical contact with a semiconductor process wafer, the blocking layer being substantially opaque to a range of wavelengths of light; applying at least one layer over the blocking layer; and inspecting optically at least one wavelength at least one inspection area, the blocking layer extending substantially throughout the inspection area. An inspection method including adhering an optical absorbing layer to a semiconductor process wafer, where the absorbing layer is configured to substantially absorb a range of wavelengths of light; applying at least one layer over the absorbing layer; and inspecting optically at least one wavelength at least one inspection area of the process wafer. A manufacturing method including ascertaining if a defect is present within a photoresist layer, and changing a semiconductor manufacturing process to prevent the defect, if the defect is present.