Patents by Inventor Sean James

Sean James has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20180267589
    Abstract: Techniques for providing backup power to distributed computing systems are disclosed herein. In one embodiment, a method includes receiving, via the computer network, data indicating a power failure of the main power source configured to provide electrical power to the servers. The method also includes instructing, via the computer network, a heating, ventilation, and air conditioning (“HVAC”) system to provide emergency power to the servers. The HVAC system includes an air mover having blades and a motor-generator mechanically coupled to the blades of the air mover. The motor-generator includes a motor that is configured to rotate the blades of the air mover and a generator that is configured to convert kinetic energy of the rotating blades of the air mover into electrical energy during a power failure of the main power source and provide the generated electrical energy as the emergency power to the servers.
    Type: Application
    Filed: March 14, 2017
    Publication date: September 20, 2018
    Inventors: Jennifer Goodward, Sean James
  • Patent number: 10072845
    Abstract: An aft heat shield for a fuel nozzle tip includes: an annular shield wall; an annular shield flange extending radially outward from an aft end of the shield wall; an annular baffle flange surrounding the conical section, and disposed such that an axial gap is defined between the shield flange and the baffle flange, the baffle flange including a radially outer rim extending axially forward therefrom; and a plurality of impingement cooling holes passing through the baffle flange and oriented to as to direct air flow towards the shield wall.
    Type: Grant
    Filed: November 15, 2013
    Date of Patent: September 11, 2018
    Assignee: GENERAL ELECTRIC COMPANY
    Inventors: Joshua Tyler Mook, Michael Anthony Benjamin, David Richard Barnhart, Sean James Henderson, Ramon Martinez, Neerav Atul Patel, Mark Richard Shaw
  • Publication number: 20180208388
    Abstract: A protectively enclosed panel of frangible thermal insulation having a panel of frangible thermal insulation with C-channel binding bars fitted over each edge of the panel and wear protective cover sheets covering the first and second major surface of the panel with the peripheral margin of the cover sheets adhered to the C-channel binding bars.
    Type: Application
    Filed: January 26, 2017
    Publication date: July 26, 2018
    Inventor: Sean James Austerberry
  • Publication number: 20180205227
    Abstract: This document relates to electricity management using modulated waveforms. One example modulates electricity to obtain modulated electricity having at least two different alternating current frequencies including a first alternating current frequency and a second alternating current frequency. The example delivers the modulated electrical power having the at least two different alternating current frequencies to multiple different electrical devices, including a first electrical device configured to utilize the first alternating current frequency and a second electrical device configured to utilize the second alternating current frequency. The modulated electricity can be delivered at least partly over an electrical line shared by the first electrical device and the second electrical device.
    Type: Application
    Filed: March 12, 2018
    Publication date: July 19, 2018
    Applicant: Microsoft Technology Licensing, LLC
    Inventors: Jie LIU, Brian JANOUS, Gregory Joseph MCKNIGHT, Sean JAMES, Ricardo BIANCHINI
  • Patent number: 9977742
    Abstract: A cache coherency controller comprises a directory indicating, for memory addresses cached by a group of two or more cache memories in a coherent cache structure, which of the cache memories are caching those memory addresses, the directory being associative so that multiple memory addresses map to an associative set of more than one directory entry; and control logic responsive to a memory address to be newly cached, and configured to detect whether one or more of the set of directory entries mapped to that memory address is available for storage of an indication of which of the two or more cache memories are caching that memory address; the control logic being configured so that when all of the set of directory entries mapped to that memory address are occupied, the control logic is configured to select one of the set of directory entries as a directory entry to be overwritten and the corresponding cached information to be invalidated, the control logic being configured to select a directory entry to be ove
    Type: Grant
    Filed: April 20, 2016
    Date of Patent: May 22, 2018
    Assignee: ARM Limited
    Inventors: Andrew David Tune, Sean James Salisbury
  • Patent number: 9954365
    Abstract: This document relates to electricity management using modulated waveforms. One example modulates electricity to obtain modulated electricity having at least two different alternating current frequencies including a first alternating current frequency and a second alternating current frequency. The example delivers the modulated electrical power having the at least two different alternating current frequencies to multiple different electrical devices, including a first electrical device configured to utilize the first alternating current frequency and a second electrical device configured to utilize the second alternating current frequency. The modulated electricity can be delivered at least partly over an electrical line shared by the first electrical device and the second electrical device.
    Type: Grant
    Filed: March 31, 2015
    Date of Patent: April 24, 2018
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Jie Liu, Brian Janous, Gregory Joseph McKnight, Sean James, Ricardo Bianchini
  • Patent number: 9933804
    Abstract: This document relates to analyzing electrical grid conditions using server installations. One example obtains first grid condition signals describing first grid conditions detected by a first server installation during a first time period. The first server installation is connected to a first electrical grid and first previous grid failure events have occurred on the first electrical grid during the first time period. The example also obtains second grid condition signals describing second grid conditions detected by a second server installation during a second time period. The second server installation is connected to a second electrical grid that is geographically remote from the first electrical grid and second previous grid failure events have occurred on the second electrical grid during the second time period. The example also includes using the first grid condition signals and the second grid condition signals to predict a future grid failure event on the second electrical grid.
    Type: Grant
    Filed: March 31, 2015
    Date of Patent: April 3, 2018
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Brian Janous, Gregory Joseph McKnight, Sean James, Ricardo Bianchini, Jie Liu
  • Patent number: 9928195
    Abstract: An interconnect, and method of operation of an interconnect, are provided for connecting a plurality of master devices and a plurality of slave devices. Hazard management circuitry is used to serialize transactions to overlapping addresses. In addition, gating circuitry ensures ordered write observation (OWO) behavior at an interface to one or more of the master devices, the gating circuitry receiving write address transfers of write transactions and performing a gating operation to gate onward propagation of the write address transfers to the slave devices in order to ensure the OWO behavior. The gating circuitry performs the gating operation under control of the hazard management circuitry. Hence, for write transactions that are subjected to hazard checking by the hazard management circuitry, this removes the need to implement any other processes to specifically manage OWO behavior for those write transactions.
    Type: Grant
    Filed: December 4, 2015
    Date of Patent: March 27, 2018
    Assignee: ARM Limited
    Inventors: Andrew David Tune, Peter Andrew Riocreux, Sean James Salisbury, Daniel Adam Sara, George Robert Scott Lloyd
  • Patent number: 9892072
    Abstract: Interconnect circuitry for connecting transaction masters to transaction slaves includes response modification circuitry. The response modification circuitry includes shortlist buffer circuitry storing identification for modification target transaction responses. The response modification circuitry uses this identification data to identify among a stream of transaction responses in transit a modification target transaction response. The response modification circuitry then serves to form a modified transaction response to be sent in place of the modification target transaction response to the transaction master.
    Type: Grant
    Filed: October 5, 2015
    Date of Patent: February 13, 2018
    Assignee: ARM Limited
    Inventors: Andrew David Tune, Arthur Brian Laughton, Daniel Adam Sara, Sean James Salisbury, Peter Andrew Riocreux
  • Patent number: 9852088
    Abstract: A system-on-check integrated circuit 2 includes interconnect circuitry 4 connecting a plurality of transaction sources to a plurality of transaction destinations. The interconnect circuitry 4 includes a reorder buffer for buffering access transactions and hazard checking circuitry 46, 48, 50, 52 for performing hazard checks, such as point-of-serialization checks and identifier reuse checks. Check suppression circuitry 62, 64, 66, 68 serves to suppress one or more hazard checks depending upon one or more state variables that themselves depend upon access transactions other than the access transaction for which the hazard checking is or is not to be suppressed. As an example, hazard checking may be suppressed if it is known that there are no other access transactions currently buffered within the reorder buffer 26 or alternatively no other access transactions from the same transaction source buffered within the reorder buffer 26.
    Type: Grant
    Filed: February 23, 2015
    Date of Patent: December 26, 2017
    Assignee: ARM Limited
    Inventors: Andrew David Tune, Daniel Sara, Sean James Salisbury, Arthur Laughton, Peter Andrew Riocreux
  • Patent number: 9812925
    Abstract: Processing units and electrical power generation are integrated with a botanical environment to form a closed loop system whereby the outputs of one component serve as the inputs of another. Additionally, humans can be added to the system while maintaining the closed loop nature. Heat generated by the electrical power generation and processing units aids in the growth of botanicals and in the conversion of waste organic materials into both fertilizer and fuel for the electrical power generation. Additionally, carbon dioxide output by the electrical power generation is consumed by the botanicals, which, in turn, output oxygen consumed by the electrical power generation. Water is obtained by passing the exhaust of the electrical power generation across condenser coils, and is utilized for adiabatic cooling, as well as a heat transfer medium. Water is also consumed by the botanicals, aiding their growth.
    Type: Grant
    Filed: July 18, 2014
    Date of Patent: November 7, 2017
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Christian L. Belady, Brian Janous, Sean James
  • Patent number: 9727466
    Abstract: An interconnect and method of managing a snoop filter within such an interconnect are provided. The interconnect is used to connect a plurality of devices, including a plurality of master devices where one or more of the master devices has an associated cache storage. The interconnect comprises coherency control circuitry to perform coherency control operations for data access transactions received by the interconnect from the master devices. In performing those operations, the coherency control circuitry has access to snoop filter circuitry that maintains address-dependent caching indication data, and is responsive to a data access transaction specifying a target address to produce snoop control data providing an indication of which master devices have cached data for the target address in their associated cache storage.
    Type: Grant
    Filed: August 11, 2015
    Date of Patent: August 8, 2017
    Assignee: ARM Limited
    Inventors: Andrew David Tune, Sean James Salisbury
  • Publication number: 20170215299
    Abstract: The subject disclosure is directed towards a submerged datacenter, which may be made up of modules, into a body of water such as the ocean. The submersion facilitates cooling of the datacenter as well as providing protection of the datacenter from environmental conditions that exist at or near the surface. Power may be generated from the datacenter heat, and power generated by or near the body of water (e.g., via waves, tides, wind, currents, temperature differences) may be used to help power the datacenter.
    Type: Application
    Filed: April 6, 2017
    Publication date: July 27, 2017
    Inventors: Sean James, Todd Robert Rawlings
  • Patent number: 9713290
    Abstract: The subject disclosure is directed towards a datacenter or partial datacenter (e.g., a datacenter module) contained in a sealed container. The container may be filled with a cooling fluid, such as a dielectric fluid, to help cool the datacenter components. The container and its internal datacenter or datacenter portion may be submerged in water, in which event the fluid also helps to equalize the external water pressure.
    Type: Grant
    Filed: June 30, 2014
    Date of Patent: July 18, 2017
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Sean James, Todd Robert Rawlings
  • Patent number: 9696981
    Abstract: Systems and methods for requesting computer software program logic by a client computing device from a server are provided. The method at the server comprises receiving a request for the computer software program logic from the client device along with a first list comprising details about multiple modules running on the client device; determining a second list comprising details about multiple modules required to deploy the computer software program logic on the client device; checking whether the modules of the second list need to be substituted based on their availability or suitability; updating the second list; checking whether the client device has permission rights for accessing the modules of the updated second list; and sending an object comprising the modules of the updated second list to the client device, the updated second list comprising details about the modules required for deployment of logic on the client device.
    Type: Grant
    Filed: April 27, 2012
    Date of Patent: July 4, 2017
    Assignee: CAMBRIDGE SEMANTICS, INC.
    Inventors: Sean James Martin, Simon Luke Martin
  • Patent number: 9655283
    Abstract: The subject disclosure is directed towards a submerged datacenter, which may be made up of modules, into a body of water such as the ocean. The submersion facilitates cooling of the datacenter as well as providing protection of the datacenter from environmental conditions that exist at or near the surface. Power may be generated from the datacenter heat, and power generated by or near the body of water (e.g., via waves, tides, wind, currents, temperature differences) may be used to help power the datacenter.
    Type: Grant
    Filed: June 30, 2014
    Date of Patent: May 16, 2017
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Sean James, Todd Robert Rawlings
  • Patent number: 9639470
    Abstract: An interconnect has coherency control circuitry for performing coherency control operations and a snoop filter for identifying which devices coupled to the interconnect have cached data from a given address. When an address is looked up in the snoop filter and misses, and there is no spare snoop filter entry available, then the snoop filter selects a victim entry corresponding to a victim address, and issues an invalidate transaction for invalidating locally cached copies of the data identified by the victim. The coherency control circuitry for performing coherency checking operations for data access transactions is reused for performing coherency control operations for the invalidate transaction issued by the snoop filter. This greatly reduces the circuitry complexity of the snoop filter.
    Type: Grant
    Filed: August 26, 2014
    Date of Patent: May 2, 2017
    Assignee: ARM Limited
    Inventors: Sean James Salisbury, Andrew David Tune, Jamshed Jalal, Mark David Werkheiser
  • Publication number: 20170003030
    Abstract: A fuel nozzle includes an outer body extending parallel to a centerline axis, having a generally cylindrical exterior surface, forward and aft ends, and a plurality of openings through the exterior surface. The fuel nozzle further includes an inner body inside the outer body, cooperating with the outer body to define an annular space, and a main injection ring inside the annular space, the main injection ring including fuel posts extending therefrom. Each fuel post is aligned with one of the openings and separated from the opening by a perimeter gap which communicates with the annular space. There is a circumferential main fuel gallery in the main injection ring, and a plurality of main fuel orifices, wherein each orifice communicates with the main fuel gallery and extends through one of the fuel posts.
    Type: Application
    Filed: December 23, 2014
    Publication date: January 5, 2017
    Inventors: Michael Anthony BENJAMIN, Joshua Tyler MOOK, Sean James HENDERSON, Ramon MARTINEZ
  • Publication number: 20160350220
    Abstract: A cache coherency controller comprises a directory indicating, for memory addresses cached by one or more of a group of one or more cache memories connectable in a coherent cache structure, which of the cache memories are caching those memory addresses; and control circuitry configured to detect a directory entry relating to a memory address to be accessed so as to coordinate, amongst the cache memories, an access to a memory address by one of the cache memories or a coherent agent in instances when the directory entry indicates that another of the cache memories is caching that memory address; the control circuitry being responsive to status data indicating whether each cache memory in the group is currently subject to cache coherency control so as to take into account, in the detection of the directory entry relating to the memory address to be accessed, only those cache memories in the group which are currently subject to cache coherency control.
    Type: Application
    Filed: April 20, 2016
    Publication date: December 1, 2016
    Inventors: Sean James SALISBURY, Andrew David TUNE
  • Publication number: 20160350219
    Abstract: A cache coherency controller comprises a directory indicating, for memory addresses cached by a group of two or more cache memories in a coherent cache structure, which of the cache memories are caching those memory addresses, the directory being associative so that multiple memory addresses map to an associative set of more than one directory entry; and control logic responsive to a memory address to be newly cached, and configured to detect whether one or more of the set of directory entries mapped to that memory address is available for storage of an indication of which of the two or more cache memories are caching that memory address; the control logic being configured so that when all of the set of directory entries mapped to that memory address are occupied, the control logic is configured to select one of the set of directory entries as a directory entry to be overwritten and the corresponding cached information to be invalidated, the control logic being configured to select a directory entry to be ove
    Type: Application
    Filed: April 20, 2016
    Publication date: December 1, 2016
    Inventors: Andrew David TUNE, Sean James SALISBURY