Abstract: A system-on-check integrated circuit 2 includes interconnect circuitry 4 connecting a plurality of transaction sources to a plurality of transaction destinations. The interconnect circuitry 4 includes a reorder buffer for buffering access transactions and hazard checking circuitry 46, 48, 50, 52 for performing hazard checks, such as point-of-serialization checks and identifier reuse checks. Check suppression circuitry 62, 64, 66, 68 serves to suppress one or more hazard checks depending upon one or more state variables that themselves depend upon access transactions other than the access transaction for which the hazard checking is or is not to be suppressed. As an example, hazard checking may be suppressed if it is known that there are no other access transactions currently buffered within the reorder buffer 26 or alternatively no other access transactions from the same transaction source buffered within the reorder buffer 26.

Abstract: Processing units and electrical power generation are integrated with a botanical environment to form a closed loop system whereby the outputs of one component serve as the inputs of another. Additionally, humans can be added to the system while maintaining the closed loop nature. Heat generated by the electrical power generation and processing units aids in the growth of botanicals and in the conversion of waste organic materials into both fertilizer and fuel for the electrical power generation. Additionally, carbon dioxide output by the electrical power generation is consumed by the botanicals, which, in turn, output oxygen consumed by the electrical power generation. Water is obtained by passing the exhaust of the electrical power generation across condenser coils, and is utilized for adiabatic cooling, as well as a heat transfer medium. Water is also consumed by the botanicals, aiding their growth.

Abstract: An interconnect and method of managing a snoop filter within such an interconnect are provided. The interconnect is used to connect a plurality of devices, including a plurality of master devices where one or more of the master devices has an associated cache storage. The interconnect comprises coherency control circuitry to perform coherency control operations for data access transactions received by the interconnect from the master devices. In performing those operations, the coherency control circuitry has access to snoop filter circuitry that maintains address-dependent caching indication data, and is responsive to a data access transaction specifying a target address to produce snoop control data providing an indication of which master devices have cached data for the target address in their associated cache storage.

Abstract: The subject disclosure is directed towards a submerged datacenter, which may be made up of modules, into a body of water such as the ocean. The submersion facilitates cooling of the datacenter as well as providing protection of the datacenter from environmental conditions that exist at or near the surface. Power may be generated from the datacenter heat, and power generated by or near the body of water (e.g., via waves, tides, wind, currents, temperature differences) may be used to help power the datacenter.

Abstract: The subject disclosure is directed towards a datacenter or partial datacenter (e.g., a datacenter module) contained in a sealed container. The container may be filled with a cooling fluid, such as a dielectric fluid, to help cool the datacenter components. The container and its internal datacenter or datacenter portion may be submerged in water, in which event the fluid also helps to equalize the external water pressure.

Abstract: Systems and methods for requesting computer software program logic by a client computing device from a server are provided. The method at the server comprises receiving a request for the computer software program logic from the client device along with a first list comprising details about multiple modules running on the client device; determining a second list comprising details about multiple modules required to deploy the computer software program logic on the client device; checking whether the modules of the second list need to be substituted based on their availability or suitability; updating the second list; checking whether the client device has permission rights for accessing the modules of the updated second list; and sending an object comprising the modules of the updated second list to the client device, the updated second list comprising details about the modules required for deployment of logic on the client device.

Abstract: The subject disclosure is directed towards a submerged datacenter, which may be made up of modules, into a body of water such as the ocean. The submersion facilitates cooling of the datacenter as well as providing protection of the datacenter from environmental conditions that exist at or near the surface. Power may be generated from the datacenter heat, and power generated by or near the body of water (e.g., via waves, tides, wind, currents, temperature differences) may be used to help power the datacenter.

Abstract: An interconnect has coherency control circuitry for performing coherency control operations and a snoop filter for identifying which devices coupled to the interconnect have cached data from a given address. When an address is looked up in the snoop filter and misses, and there is no spare snoop filter entry available, then the snoop filter selects a victim entry corresponding to a victim address, and issues an invalidate transaction for invalidating locally cached copies of the data identified by the victim. The coherency control circuitry for performing coherency checking operations for data access transactions is reused for performing coherency control operations for the invalidate transaction issued by the snoop filter. This greatly reduces the circuitry complexity of the snoop filter.

Abstract: A fuel nozzle includes an outer body extending parallel to a centerline axis, having a generally cylindrical exterior surface, forward and aft ends, and a plurality of openings through the exterior surface. The fuel nozzle further includes an inner body inside the outer body, cooperating with the outer body to define an annular space, and a main injection ring inside the annular space, the main injection ring including fuel posts extending therefrom. Each fuel post is aligned with one of the openings and separated from the opening by a perimeter gap which communicates with the annular space. There is a circumferential main fuel gallery in the main injection ring, and a plurality of main fuel orifices, wherein each orifice communicates with the main fuel gallery and extends through one of the fuel posts.

Abstract: A cache coherency controller comprises a directory indicating, for memory addresses cached by one or more of a group of one or more cache memories connectable in a coherent cache structure, which of the cache memories are caching those memory addresses; and control circuitry configured to detect a directory entry relating to a memory address to be accessed so as to coordinate, amongst the cache memories, an access to a memory address by one of the cache memories or a coherent agent in instances when the directory entry indicates that another of the cache memories is caching that memory address; the control circuitry being responsive to status data indicating whether each cache memory in the group is currently subject to cache coherency control so as to take into account, in the detection of the directory entry relating to the memory address to be accessed, only those cache memories in the group which are currently subject to cache coherency control.

Abstract: A cache coherency controller comprises a directory indicating, for memory addresses cached by a group of two or more cache memories in a coherent cache structure, which of the cache memories are caching those memory addresses, the directory being associative so that multiple memory addresses map to an associative set of more than one directory entry; and control logic responsive to a memory address to be newly cached, and configured to detect whether one or more of the set of directory entries mapped to that memory address is available for storage of an indication of which of the two or more cache memories are caching that memory address; the control logic being configured so that when all of the set of directory entries mapped to that memory address are occupied, the control logic is configured to select one of the set of directory entries as a directory entry to be overwritten and the corresponding cached information to be invalidated, the control logic being configured to select a directory entry to be ove

Abstract: An interconnect has coherency control circuitry for performing coherency control operations and a snoop filter for identifying which devices coupled to the interconnect have cached data from a given address. When an address is looked up in the snoop filter and misses, and there is no spare snoop filter entry available, then the snoop filter selects a victim entry corresponding to a victim address, and issues an invalidate transaction for invalidating locally cached copies of the data identified by the victim. The coherency control circuitry for performing coherency checking operations for data access transactions is reused for performing coherency control operations for the invalidate transaction issued by the snoop filter. This greatly reduces the circuitry complexity of the snoop filter.

Abstract: An orthotic device is disclosed having a frame system, a first actuator, and a second actuator. The frame system may include a lightweight supportive material, and may be configured to receive a user's foot. The first actuator may be coupled to the frame system, and may be configured to activate and develop push of the forefoot of the user's foot during a walking step. The second actuator may be coupled to the frame system, and may be configured to activate and raise a user's toes.

Abstract: There is provided an interconnect for transferring requests between ports in which the ports include both source ports destination ports. The interconnect includes storage circuitry for storing the requests. Input circuitry receives the requests from the plurality of source ports, selects at least one selected source port from an allowed set of said plurality of source ports, and transfers a presented request from the at least one selected source port to the storage circuitry. Output circuitry causes a request in said storage circuitry to be output at one of said plurality of destination ports. Counter circuitry maintains counter values for a plurality of tracked ports from amongst said ports, each counter value indicating the number of requests in said storage circuitry associated with a corresponding tracked port that are waiting to be output by said output circuitry and filter circuitry determines whether or not a given source port is in said allowed set in dependence on said counter circuitry.

Abstract: An interconnect, and method of operation of an interconnect, are provided for connecting a plurality of master devices and a plurality of slave devices. Hazard management circuitry is used to serialise transactions to overlapping addresses. In addition, gating circuitry ensures ordered write observation (OWO) behaviour at an interface to one or more of the master devices, the gating circuitry receiving write address transfers of write transactions and performing a gating operation to gate onward propagation of the write address transfers to the slave devices in order to ensure the OWO behaviour. The gating circuitry performs the gating operation under control of the hazard management circuitry. Hence, for write transactions that are subjected to hazard checking by the hazard management circuitry, this removes the need to implement any other processes to specifically manage OWO behaviour for those write transactions.

Abstract: A data array has multiple ways, each way having entries for storing data values. In response to a write request, an updated data value having a target address may be stored in any of a corresponding set of entries comprising an entry selected from each way based on the target address. An update queue stores update information representing pending write requests. Update information is selected from the update queue for a group of pending write requests corresponding to different ways, and these write requests are performed in parallel so that updated values are written to entries of different ways.

Abstract: Interconnect circuitry 10 for connecting transaction masters 4, 6, 8 to transaction slaves 12, 14 includes response modification circuitry 18. The response modification circuitry includes shortlist buffer circuitry 28 storing identification for modification target transaction responses. The response modification circuitry 18 uses this identification data to identify among a stream of transaction responses in transit a modification target transaction response. The response modification circuitry 18 then serves to form a modified transaction response to be sent in place of the modification target transaction response to the transaction master 4, 6, 8.

Abstract: An interconnect has transaction tracking circuitry for enforcing ordering of a set of data access transactions so that they are issued to slave devices in an order in which they are received from master devices. The transaction tracking circuitry is reused for also enforcing ordering of snoop transactions which are triggered by the set of data access transactions, for snooping master devices identified by a snoop filter as holding cache data for the target address of the transactions.

Abstract: An arbiter is configured to select one of several contending data packets transmitted from an initiator, the data packets comprising an identifier identifying the initiator and data. The arbiter comprises: a history buffer for storing the identifiers identifying the initiators of a plurality of recently selected data packets; and selection circuitry configured to select one of the contending data packets in dependence upon the initiators of the contending data packets and the initiators identified in the history buffer, such that a probability of a data packet being selected increases with the number of data packets selected since a data packet from the same initiator was selected.

Abstract: Disclosed is a dasher-boards assembly with capability to absorb impacts of players crashing into the boards. The glass pane surmounting the boards can tip away from the ice, against a spring, and then resiliently return to its normal (upright) position. The spring is a bar-spring, which not only is deflectable to provide the resilience, but also has the capability to support and position the pane with respect to the dasher-board. The bar-spring can be used when the pane is flush-mounted with respect to the dasher-board, or when the pane is set-back from the ice-side of the dasher-board.