Patents by Inventor Sean James

Sean James has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20160203094
    Abstract: There is provided an interconnect for transferring requests between ports in which the ports include both source ports destination ports. The interconnect includes storage circuitry for storing the requests. Input circuitry receives the requests from the plurality of source ports, selects at least one selected source port from an allowed set of said plurality of source ports, and transfers a presented request from the at least one selected source port to the storage circuitry. Output circuitry causes a request in said storage circuitry to be output at one of said plurality of destination ports. Counter circuitry maintains counter values for a plurality of tracked ports from amongst said ports, each counter value indicating the number of requests in said storage circuitry associated with a corresponding tracked port that are waiting to be output by said output circuitry and filter circuitry determines whether or not a given source port is in said allowed set in dependence on said counter circuitry.
    Type: Application
    Filed: November 18, 2015
    Publication date: July 14, 2016
    Inventors: Andrew David TUNE, Sean James SALISBURY
  • Patent number: 9361236
    Abstract: A data array has multiple ways, each way having entries for storing data values. In response to a write request, an updated data value having a target address may be stored in any of a corresponding set of entries comprising an entry selected from each way based on the target address. An update queue stores update information representing pending write requests. Update information is selected from the update queue for a group of pending write requests corresponding to different ways, and these write requests are performed in parallel so that updated values are written to entries of different ways.
    Type: Grant
    Filed: June 18, 2013
    Date of Patent: June 7, 2016
    Assignee: ARM Limited
    Inventors: Andrew David Tune, Sean James Salisbury
  • Publication number: 20160103776
    Abstract: Interconnect circuitry 10 for connecting transaction masters 4, 6, 8 to transaction slaves 12, 14 includes response modification circuitry 18. The response modification circuitry includes shortlist buffer circuitry 28 storing identification for modification target transaction responses. The response modification circuitry 18 uses this identification data to identify among a stream of transaction responses in transit a modification target transaction response. The response modification circuitry 18 then serves to form a modified transaction response to be sent in place of the modification target transaction response to the transaction master 4, 6, 8.
    Type: Application
    Filed: October 5, 2015
    Publication date: April 14, 2016
    Inventors: Andrew David TUNE, Arthur Brian LAUGHTON, Daniel Adam SARA, Sean James SALISBURY, Peter Andrew RIOCREUX
  • Patent number: 9311244
    Abstract: An interconnect has transaction tracking circuitry for enforcing ordering of a set of data access transactions so that they are issued to slave devices in an order in which they are received from master devices. The transaction tracking circuitry is reused for also enforcing ordering of snoop transactions which are triggered by the set of data access transactions, for snooping master devices identified by a snoop filter as holding cache data for the target address of the transactions.
    Type: Grant
    Filed: August 25, 2014
    Date of Patent: April 12, 2016
    Assignee: ARM Limited
    Inventors: Sean James Salisbury, Andrew David Tune, Daniel Sara
  • Patent number: 9294301
    Abstract: An arbiter is configured to select one of several contending data packets transmitted from an initiator, the data packets comprising an identifier identifying the initiator and data. The arbiter comprises: a history buffer for storing the identifiers identifying the initiators of a plurality of recently selected data packets; and selection circuitry configured to select one of the contending data packets in dependence upon the initiators of the contending data packets and the initiators identified in the history buffer, such that a probability of a data packet being selected increases with the number of data packets selected since a data packet from the same initiator was selected.
    Type: Grant
    Filed: September 20, 2012
    Date of Patent: March 22, 2016
    Assignee: ARM Limited
    Inventors: Andrew David Tune, Sean James Salisbury, Alistair Crone Bruce
  • Patent number: 9283469
    Abstract: Disclosed is a dasher-boards assembly with capability to absorb impacts of players crashing into the boards. The glass pane surmounting the boards can tip away from the ice, against a spring, and then resiliently return to its normal (upright) position. The spring is a bar-spring, which not only is deflectable to provide the resilience, but also has the capability to support and position the pane with respect to the dasher-board. The bar-spring can be used when the pane is flush-mounted with respect to the dasher-board, or when the pane is set-back from the ice-side of the dasher-board.
    Type: Grant
    Filed: April 22, 2013
    Date of Patent: March 15, 2016
    Assignee: 1196501 ONTARIO INC.
    Inventors: Terence William Riley, Sean James Riley
  • Publication number: 20160062893
    Abstract: An interconnect and method of managing a snoop filter within such an interconnect are provided. The interconnect is used to connect a plurality of devices, including a plurality of master devices where one or more of the master devices has an associated cache storage. The interconnect comprises coherency control circuitry to perform coherency control operations for data access transactions received by the interconnect from the master devices. In performing those operations, the coherency control circuitry has access to snoop filter circuitry that maintains address-dependent caching indication data, and is responsive to a data access transaction specifying a target address to produce snoop control data providing an indication of which master devices have cached data for the target address in their associated cache storage.
    Type: Application
    Filed: August 11, 2015
    Publication date: March 3, 2016
    Inventors: Andrew David TUNE, Sean James SALISBURY
  • Publication number: 20160062889
    Abstract: An interconnect has coherency control circuitry for performing coherency control operations and a snoop filter for identifying which devices coupled to the interconnect have cached data from a given address. When an address is looked up in the snoop filter and misses, and there is no spare snoop filter entry available, then the snoop filter selects a victim entry corresponding to a victim address, and issues an invalidate transaction for invalidating locally cached copies of the data identified by the victim. The coherency control circuitry for performing coherency checking operations for data access transactions is reused for performing coherency control operations for the invalidate transaction issued by the snoop filter. This greatly reduces the circuitry complexity of the snoop filter.
    Type: Application
    Filed: August 26, 2014
    Publication date: March 3, 2016
    Inventors: Sean James SALISBURY, Andrew David TUNE, Jamshed JALAL, Mark David WERKHEISER
  • Publication number: 20160062890
    Abstract: An interconnect has coherency control circuitry for performing coherency control operations and a snoop filter for identifying which devices coupled to the interconnect have cached data from a given address. When an address is looked up in the snoop filter and misses, and there is no spare snoop filter entry available, then the snoop filter selects a victim entry corresponding to a victim address, and issues an invalidate transaction for invalidating locally cached copies of the data identified by the victim. The coherency control circuitry for performing coherency checking operations for data access transactions is reused for performing coherency control operations for the invalidate transaction issued by the snoop filter. This greatly reduces the circuitry complexity of the snoop filter.
    Type: Application
    Filed: March 6, 2015
    Publication date: March 3, 2016
    Inventors: Sean James SALISBURY, Andrew David TUNE, Jamshed JALAL, Mark David WERKHEISER, Arthur LAUGHTON, George Robert Scott LLOYD, Peter Andrew RIOCREUX, Daniel SARA
  • Publication number: 20160055085
    Abstract: An interconnect has transaction tracking circuitry for enforcing ordering of a set of data access transactions so that they are issued to slave devices in an order in which they are received from master devices. The transaction tracking circuitry is reused for also enforcing ordering of snoop transactions which are triggered by the set of data access transactions, for snooping master devices identified by a snoop filter as holding cache data for the target address of the transactions.
    Type: Application
    Filed: August 25, 2014
    Publication date: February 25, 2016
    Inventors: Sean James SALISBURY, Andrew David TUNE, Daniel SARA
  • Publication number: 20160020669
    Abstract: Processing units and electrical power generation are integrated with a botanical environment to form a closed loop system whereby the outputs of one component serve as the inputs of another. Additionally, humans can be added to the system while maintaining the closed loop nature. Heat generated by the electrical power generation and processing units aids in the growth of botanicals and in the conversion of waste organic materials into both fertilizer and fuel for the electrical power generation. Additionally, carbon dioxide output by the electrical power generation is consumed by the botanicals, which, in turn, output oxygen consumed by the electrical power generation. Water is obtained by passing the exhaust of the electrical power generation across condenser coils, and is utilized for adiabatic cooling, as well as a heat transfer medium. Water is also consumed by the botanicals, aiding their growth.
    Type: Application
    Filed: July 18, 2014
    Publication date: January 21, 2016
    Inventors: Christian L. Belady, Brian Janous, Sean James
  • Publication number: 20160004263
    Abstract: Electrical power is provided to power consuming, heat-exhausting devices by multiple gas-fueled electrical power sources located near such devices. Exhaust heat from such devices is utilized as intake cooling air for the gas-fueled power sources, thereby excluding them from cooling capacity requirements. The gas piping delivering gas to gas-fueled power sources is positioned so as to be within hot aisles comprising exhaust heat. The gas piping is located up high for lighter than air gasses and near the floor for heavier than air gasses, with leak detection located nearby. Additionally, gas piping is externally coated with material that visually indicates a leak. By locating gas piping in the hot aisle, exhausted heat increases temperature and, thereby, pressure of the gas, resulting in more efficient gas distribution through the piping and preventing valve freezing. Furthermore, the gas piping is located after potential ignition sources in the airstream.
    Type: Application
    Filed: July 2, 2014
    Publication date: January 7, 2016
    Inventors: Sean James, Christian L. Belady, Stephan W. Gilges, Sriram Sankar, John Siegler, Brian Andersen, Eric C. Peterson, J Darrin Schroeder
  • Publication number: 20150376031
    Abstract: Waste heat generated by devices as a byproduct of their operation is utilized to increase and maintain the temperature of non-potable water to neutralize biological contaminants, thereby rendering such water potable. The potable water can then be utilized for evaporative cooling of the devices. A temperature sensor monitors the temperature of the non-potable water and a controller controls the pump to provide sufficient time for the water to remain in the heat exchanger above a predetermined temperature to neutralize biological contaminants and render such water potable. To the extent that different devices generate different quantities and intensities of waste heat, multiple heat exchangers are utilized, with lower intensity waste heat serving to preheat the water and, thereby, reduce the amount of time needed to reach the target temperature in a primary heat exchanger. Waste heat not utilized to generate potable water can be utilized for other heat-driven processes.
    Type: Application
    Filed: June 27, 2014
    Publication date: December 31, 2015
    Inventor: Sean James
  • Publication number: 20150382515
    Abstract: The subject disclosure is directed towards a datacenter or partial datacenter (e.g., a datacenter module) contained in a sealed container. The container may be filled with a cooling fluid, such as a dielectric fluid, to help cool the datacenter components. The container and its internal datacenter or datacenter portion may be submerged in water, in which event the fluid also helps to equalize the external water pressure.
    Type: Application
    Filed: June 30, 2014
    Publication date: December 31, 2015
    Inventors: Sean James, Todd Robert Rawlings
  • Publication number: 20150382511
    Abstract: The subject disclosure is directed towards a submerged datacenter, which may be made up of modules, into a body of water such as the ocean. The submersion facilitates cooling of the datacenter as well as providing protection of the datacenter from environmental conditions that exist at or near the surface. Power may be generated from the datacenter heat, and power generated by or near the body of water (e.g., via waves, tides, wind, currents, temperature differences) may be used to help power the datacenter.
    Type: Application
    Filed: June 30, 2014
    Publication date: December 31, 2015
    Inventors: Sean James, Todd Robert Rawlings
  • Patent number: 9213660
    Abstract: A data processing apparatus is provided with a master device and a slave device which communicate via communication circuitry. The slave device is associated with a predetermined number of permission tokens that is equal to a maximum number of currently pending messages that can be accepted for processing from the communication circuitry by that slave device. The slave device transmits these permission tokens to the master device. The master device takes exclusive temporary possession of the permission tokens that it receives such that the permission tokens are then no longer available to any other master device. A master device initiates a message to a slave device when the master device has exclusive temporary possession of a permission token for that slave device. When the master device has initiated its message, then it relinquishes the exclusive temporary possession of the permission token such that it is then available for other devices.
    Type: Grant
    Filed: June 14, 2013
    Date of Patent: December 15, 2015
    Assignee: ARM Limited
    Inventors: Sean James Salisbury, Andrew David Tune, Alistair Crone Bruce
  • Patent number: 9170979
    Abstract: An integrated circuit includes one or more transaction data sources and one or more transaction data destinations connected via interconnect circuitry comprising a plurality of interconnect nodes. Within the interconnect nodes there are one or more converging interconnect nodes. A converging interconnect node includes prediction data generation circuitry for reading characteristics of a current item of transaction data from the converging interconnect node and generating associated prediction data for a future item of transaction data which will be returned to the converging interconnect node at a predetermined time in the future. This prediction data is stored within prediction data storage circuitry and is read by prediction data evaluation circuitry to control processing of a future item of transaction data corresponding to that prediction data when it is returned to the converging interconnect node. The interconnect circuitry may have a branching network topology or recirculating ring based topology.
    Type: Grant
    Filed: March 23, 2012
    Date of Patent: October 27, 2015
    Assignee: ARM Limited
    Inventors: Sean James Salisbury, Andrew David Tune
  • Publication number: 20150301961
    Abstract: A system-on-check integrated circuit 2 includes interconnect circuitry 4 connecting a plurality of transaction sources to a plurality of transaction destinations. The interconnect circuitry 4 includes a reorder buffer for buffering access transactions and hazard checking circuitry 46, 48, 50, 52 for performing hazard checks, such as point-of-serialisation checks and identifier reuse checks. Check suppression circuitry 62, 64, 66, 68 serves to suppress one or more hazard checks depending upon one or more state variables that themselves depend upon access transactions other than the access transaction for which the hazard checking is or is not to be suppressed. As an example, hazard checking may be suppressed if it is known that there are no other access transactions currently buffered within the reorder buffer 26 or alternatively no other access transactions from the same transaction source buffered within the reorder buffer 26.
    Type: Application
    Filed: February 23, 2015
    Publication date: October 22, 2015
    Inventors: Andrew David TUNE, Daniel SARA, Sean James SALISBURY, Arthur LAUGHTON, Peter Andrew RIOCREUX
  • Publication number: 20150292743
    Abstract: An aft heat shield for a fuel nozzle tip includes: an annular shield wall; an annular shield flange extending radially outward from an aft end of the shield wall; an annular baffle flange surrounding the conical section, and disposed such that an axial gap is defined between the shield flange and the baffle flange, the baffle flange including a radially outer rim extending axially forward therefrom; and a plurality of impingement cooling holes passing through the baffle flange and oriented to as to direct air flow towards the shield wall.
    Type: Application
    Filed: November 15, 2013
    Publication date: October 15, 2015
    Applicant: GENERAL ELECTRIC COMPANY
    Inventors: Joshua Tyler Mook, Michael Anthony Benjamin, David Richard Barnhart, Sean James Henderson, Ramon Martinez, Neerav Atul Patel, Mark Richard Shaw
  • Patent number: D734040
    Type: Grant
    Filed: August 4, 2014
    Date of Patent: July 14, 2015
    Assignee: MERRICK ENGINEERING, INC.
    Inventors: Abraham Abdi, Kasin Chan, Sean James Dinsmore