Patents by Inventor Sean M. Seutter
Sean M. Seutter has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 12322633Abstract: Embodiments of the disclosure provide electrostatic chucks for securing substrates during processing. Some embodiments of this disclosure provide methods and apparatus for increased temperature control across the radial profile of the substrate. Some embodiments of the disclosure provide methods and apparatus for providing control of hydrogen concentration in processed films during a high-density plasma (HDP) process.Type: GrantFiled: July 6, 2021Date of Patent: June 3, 2025Assignee: Applied Materials, Inc.Inventors: Hanish Kumar Panavalappil Kumarankutty, Sean M. Seutter, Sudhir R. Gondhalekar, Wendell Glenn Boyd, Jr., Badri Ramamurthi, Shekhar Athani, Anil Kumar Kalal, Jay Dee Pinson, II
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Publication number: 20240110284Abstract: A method of processing a substrate is disclosed which includes depositing a layer in a processing chamber on a field region, a sidewall region, and a fill region of a feature of the substrate, wherein a hardness of a portion of the layer deposited on the sidewall region is lower than a hardness of a portion of the layer deposited on the field region, and lower than a hardness of a portion of the layer deposited on the fill region.Type: ApplicationFiled: September 26, 2023Publication date: April 4, 2024Inventors: Lulu XIONG, Kevin Hsiao, Chris LIU, Chieh-Wen LO, Sean M. SEUTTER, Deenesh PADHI, Prayudi LIANTO, Peng SUO, Guan Huei SEE, Zongbin WANG, Shengwei ZENG, Balamurugan RAMASAMY
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Publication number: 20230037450Abstract: Films are modified to include deuterium in an inductive high density plasma chamber. Chamber hardware designs enable tunability of the deuterium concentration uniformity in the film across a substrate. Manufacturing of solid state electronic devices include integrated process flows to modify a film that is substantially free of hydrogen and deuterium to include deuterium.Type: ApplicationFiled: October 18, 2022Publication date: February 9, 2023Applicant: Applied Materials, Inc.Inventors: Sean M. Seutter, Mun Kyu Park, Hien M Le, Chih-Chiang Chuang
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Patent number: 11508584Abstract: Films are modified to include deuterium in an inductive high density plasma chamber. Chamber hardware designs enable tunability of the deuterium concentration uniformity in the film across a substrate. Manufacturing of solid state electronic devices include integrated process flows to modify a film that is substantially free of hydrogen and deuterium to include deuterium.Type: GrantFiled: June 12, 2020Date of Patent: November 22, 2022Assignee: Applied Materials, Inc.Inventors: Sean M. Seutter, Mun Kyu Park, Hien M Le, Chih-Chiang Chuang
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Patent number: 11462411Abstract: A semiconductor device fabrication process includes forming gates on a substrate having a plurality of openings, each gate having a conducting layer a first metal and a gate dielectric layer of a first dielectric material, partially filling the openings with a second dielectric material, forming a first structure on the substrate in a processing system without breaking vacuum, depositing a third dielectric material over the first structure, and forming a planarized surface of the gates and a surface of the third dielectric material that is disposed over the first structure. The forming of the first structure includes forming trenches by removing second portions of the second dielectric material within each opening, forming recessed active regions in the trenches by partially filling the trenches with a second metal, forming a liner over each recessed active region, and forming a metal cap layer over each liner.Type: GrantFiled: April 28, 2021Date of Patent: October 4, 2022Assignee: APPLIED MATERIALS, INC.Inventors: Gaurav Thareja, Keyvan Kashefizadeh, Xikun Wang, Anchuan Wang, Sanjay Natarajan, Sean M. Seutter, Dong Wu
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Patent number: 11370669Abstract: Amorphous silicon doped yttrium oxide films and methods of making same are described. Deposition of the amorphous silicon doped yttrium oxide film by thermal chemical vapor deposition or atomic layer deposition process are described.Type: GrantFiled: January 14, 2019Date of Patent: June 28, 2022Assignee: Applied Materials, Inc.Inventors: Tatsuya E. Sato, Li-Qun Xia, Sean M. Seutter
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Publication number: 20220005723Abstract: Embodiments of the disclosure provide electrostatic chucks for securing substrates during processing. Some embodiments of this disclosure provide methods and apparatus for increased temperature control across the radial profile of the substrate. Some embodiments of the disclosure provide methods and apparatus for providing control of hydrogen concentration in processed films during a high-density plasma (HDP) process.Type: ApplicationFiled: July 6, 2021Publication date: January 6, 2022Applicant: Applied Materials, Inc.Inventors: Hanish Kumar Panavalappil Kumarankutty, Sean M. Seutter, Sudhir R. Gondhalekar, Wendell Glenn Boyd, JR., Badri Ramamurthi, Shekhar Athani, Anil Kumar Kalal, Jay Dee Pinson, II
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Publication number: 20210249270Abstract: A semiconductor device fabrication process includes forming gates on a substrate having a plurality of openings, each gate having a conducting layer a first metal and a gate dielectric layer of a first dielectric material, partially filling the openings with a second dielectric material, forming a first structure on the substrate in a processing system without breaking vacuum, depositing a third dielectric material over the first structure, and forming a planarized surface of the gates and a surface of the third dielectric material that is disposed over the first structure. The forming of the first structure includes forming trenches by removing second portions of the second dielectric material within each opening, forming recessed active regions in the trenches by partially filling the trenches with a second metal, forming a liner over each recessed active region, and forming a metal cap layer over each liner.Type: ApplicationFiled: April 28, 2021Publication date: August 12, 2021Inventors: Gaurav THAREJA, Keyvan KASHEFIZADEH, Xikun WANG, Anchuan WANG, Sanjay NATARAJAN, Sean M. SEUTTER, Dong WU
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Patent number: 11004687Abstract: A semiconductor device fabrication process includes forming gates on a substrate having a plurality of openings, each gate having a conducting layer a first metal and a gate dielectric layer of a first dielectric material, partially filling the openings with a second dielectric material, forming a first structure on the substrate in a processing system without breaking vacuum, depositing a third dielectric material over the first structure, and forming a planarized surface of the gates and a surface of the third dielectric material that is disposed over the first structure. The forming of the first structure includes forming trenches by removing second portions of the second dielectric material within each opening, forming recessed active regions in the trenches by partially filling the trenches with a second metal, forming a liner over each recessed active region, and forming a metal cap layer over each liner.Type: GrantFiled: June 17, 2019Date of Patent: May 11, 2021Assignee: APPLIED MATERIALS, INC.Inventors: Gaurav Thareja, Keyvan Kashefizadeh, Xikun Wang, Anchuan Wang, Sanjay Natarajan, Sean M. Seutter, Dong Wu
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Publication number: 20200395218Abstract: Films are modified to include deuterium in an inductive high density plasma chamber. Chamber hardware designs enable tunability of the deuterium concentration uniformity in the film across a substrate. Manufacturing of solid state electronic devices include integrated process flows to modify a film that is substantially free of hydrogen and deuterium to include deuterium.Type: ApplicationFiled: June 12, 2020Publication date: December 17, 2020Applicant: Applied Materials, Inc.Inventors: Sean M. Seutter, Mun Kyu Park, Hien M Le, Chih-Chiang Chuang
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Publication number: 20200258744Abstract: A semiconductor device fabrication process includes forming gates on a substrate having a plurality of openings, each gate having a conducting layer a first metal and a gate dielectric layer of a first dielectric material, partially filling the openings with a second dielectric material, forming a first structure on the substrate in a processing system without breaking vacuum, depositing a third dielectric material over the first structure, and forming a planarized surface of the gates and a surface of the third dielectric material that is disposed over the first structure. The forming of the first structure includes forming trenches by removing second portions of the second dielectric material within each opening, forming recessed active regions in the trenches by partially filling the trenches with a second metal, forming a liner over each recessed active region, and forming a metal cap layer over each liner.Type: ApplicationFiled: June 17, 2019Publication date: August 13, 2020Inventors: Gaurav THAREJA, Keyvan KASHEFIZADEH, Xikun WANG, Anchuan WANG, Sanjay NATARAJAN, Sean M. SEUTTER, Dong Wu
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Publication number: 20190221426Abstract: Amorphous silicon doped yttrium oxide films and methods of making same are described. Deposition of the amorphous silicon doped yttrium oxide film by thermal chemical vapor deposition or atomic layer deposition process are described.Type: ApplicationFiled: January 14, 2019Publication date: July 18, 2019Inventors: Tatsuya E. Sato, Li-Qun Xia, Sean M. Seutter
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Patent number: 10181535Abstract: Fabrication methods and structures relating to backplanes for back contact solar cells that provide for solar cell substrate reinforcement and electrical interconnects are described. The method comprises depositing an interdigitated pattern of base electrodes and emitter electrodes on a backside surface of a semiconductor substrate, forming electrically conductive emitter plugs and base plugs on the interdigitated pattern, and attaching a backplane having a second interdigitated pattern of base electrodes and emitter electrodes at the conductive emitter and base plugs to form electrical interconnects.Type: GrantFiled: February 2, 2015Date of Patent: January 15, 2019Assignee: Tesla, Inc.Inventors: Mehrdad M. Moslehi, David Xuan-Qi Wang, Karl-Josef Kramer, Sean M. Seutter, Sam Tone Tor, Anthony Calcaterra
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Patent number: 9929054Abstract: Methods and systems are provided for the split and separation of a layer of desired thickness of crystalline semiconductor material containing optical, photovoltaic, electronic, micro-electro-mechanical system (MEMS), or optoelectronic devices, from a thicker donor wafer using laser irradiation.Type: GrantFiled: December 14, 2015Date of Patent: March 27, 2018Inventors: Takao Yonehara, Virendra V. Rana, Sean M. Seutter, Mehrdad M. Moslehi, Subramanian Tamilmani
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Patent number: 9892941Abstract: Apparatus, reactors, and methods for heating substrates are disclosed. The apparatus comprises a stage comprising a body and a surface having an area to support a substrate, a shaft coupled to the stage, a first heating element disposed within a central region of the body of the stage, and at least second and third heating elements disposed within the body of the stage, the at least second and third heating elements each partially surrounding the first heating element and wherein the at least second and third heating elements are circumferentially adjacent to each other.Type: GrantFiled: June 16, 2009Date of Patent: February 13, 2018Assignee: Applied Materials, Inc.Inventors: Anqing Cui, Binh Tran, Alexander Tam, Jacob W. Smith, R. Suryanarayanan Iyer, Joseph Yudovsky, Sean M. Seutter
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Patent number: 9806220Abstract: A back contact solar cell is described which includes a semiconductor light absorbing layer; a first-level metal layer (M1), the M1 metal layer on a back side of the light absorbing layer, the back side being opposite from a front side of the light absorbing layer designed to receive incident light; an electrically insulating backplane sheet backside of said solar cell with the M1 layer, the backplane sheet comprising a plurality of via holes that expose portions of the M1 layer beneath the backplane sheet; and an M2 layer in contact with the backplane sheet, the M2 layer made of a sheet of pre-fabricated metal foil material comprising a thickness of between 5-250 ?m, the M2 layer electrically connected to the M1 layer through the via holes in the backplane sheet.Type: GrantFiled: November 12, 2014Date of Patent: October 31, 2017Assignee: OB REALTY, LLCInventors: Mehrdad M. Moslehi, Thom Stalcup, Karl-Josef Kramer, Anthony Calcaterra, Virendra V. Rana, Sean M. Seutter, Pawan Kapur, Michael Wingert
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Patent number: 9799522Abstract: The present application provides effective and efficient structures and methods for the formation of solar cell base and emitter regions and passivation layers using laser processing. Laser absorbent passivation materials are formed on a solar cell substrate and patterned using laser ablation to form base and emitter regions. Laser damage to the solar cell substrate is removed using an etch.Type: GrantFiled: February 26, 2015Date of Patent: October 24, 2017Assignee: OB REALTY, LLCInventors: Pawan Kapur, Anand Deshpande, Sean M. Seutter, Heather Deshazer, Virendra V. Rana, Solene Coutant, Swaroop Kommera, Mehrdad M. Moslehi
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Publication number: 20170287715Abstract: The present application provides effective and efficient structures and methods for the formation of solar cell base and emitter regions and passivation layers using laser processing. Laser absorbent passivation materials are formed on a solar cell substrate and patterned using laser ablation to form base and emitter regions.Type: ApplicationFiled: April 19, 2017Publication date: October 5, 2017Inventors: Heather Deshazer, Virendra V. Rana, Sean M. Seutter, Pawan Kapur, Mehrdad M. Moslehi, Solene Coutant
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Patent number: 9768343Abstract: Laser patterning methods utilize a laser absorbent hard mask in combination with wet etching to form patterned solar cell doped regions to improve cell efficiency by avoiding laser ablation of an underlying semiconductor substrate associated with ablation of an overlying transparent passivation layer.Type: GrantFiled: April 29, 2014Date of Patent: September 19, 2017Assignee: OB Realty, LLC.Inventors: Virendra V. Rana, Pawan Kapur, Sean M. Seutter, Mehrdad M. Moslehi
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Publication number: 20170236954Abstract: Fabrication methods and structures relating to multi-level metallization for solar cells as well as fabrication methods and structures for forming back contact solar cells are provided.Type: ApplicationFiled: April 3, 2017Publication date: August 17, 2017Inventors: Karl-Josef Kramer, Mehrdad M. Moslehi, Pawan Kapur, Virendra V. Rana, David Dutton, Sean M. Seutter, Anthony Calcaterra, Jay Ashjaee, Takao Yonehara