Abstract: An integrated circuit wafer is produced to include a substrate comprising a conductive layer and an insulating layer. The wafer can further be produced to include one or more circuit TSVs formed at least partially through the substrate and associated with an integrated circuit (IC). A test structure configured to facilitate testing of the integrity of the one or more circuit TSVs can be formed on the wafer. The test structure can include a first test TSV formed one of partially through the insulating layer, or through the insulating layer and partially through the conductive layer of the substrate, and a second test TSV formed one of partially through the insulating layer, or through the insulating layer and partially through the conductive layer of the substrate. The first test TSV and the second test TSV can operate as witness TSVs to the operability of the circuit TSVs.

Abstract: Methods and apparatus for an assembly having directly bonded first and second wafers where the assembly includes a backside surface and a front side surface. The first wafer includes IO signal connections vertically routed to the direct bonding interface by a first one of the bonding posts on the first wafer bonded to a first one of the bonding posts on the second wafer. The second wafer includes vertical routing of the IO signal connections from first one though the bonding posts on the second wafer to IO pads on a backside surface of the assembly.

Abstract: A scalable independent unit cell device architecture may include a phase-shifting element and a phase shift driver both integrated within the unit cell device. The phase shift driver may be coupled to the phase-shifting element and the phase shift driver may independently control the phase-shifting element to produce an optical beam having a desired phase. The unit cell device may further include an optical antenna that outputs the beam having the desired phase. The unit cell device may be formed as an opto-electronic hybrid optimized to leverage direct bond hybridization (DBH) to attach an electronic integrated circuit wafer to a side of a photonic integrated circuit wafer. The resulting unit cell device (i.e., 24 microns) may tightly integrate individual element-level phase control, which may be implemented within large-scale two-dimensional photonic arrays with hemispherical beam steering.

Abstract: Methods and apparatus for an assembly having directly bonded first and second wafers where the assembly includes a backside surface and a front side surface. The first wafer includes IO signal connections vertically routed to the direct bonding interface by a first one of the bonding posts on the first wafer bonded to a first one of the bonding posts on the second wafer. The second wafer includes vertical routing of the IO signal connections from first one though the bonding posts on the second wafer to IO pads on a backside surface of the assembly.

Abstract: A scalable independent unit cell device architecture may include a phase-shifting element and a phase shift driver both integrated within the unit cell device. The phase shift driver may be coupled to the phase-shifting element and the phase shift driver may independently control the phase-shifting element to produce an optical beam having a desired phase. The unit cell device may further include an optical antenna that outputs the beam having the desired phase. The unit cell device may be formed as an opto-electronic hybrid optimized to leverage direct bond hybridization (DBH) to attach an electronic integrated circuit wafer to a side of a photonic integrated circuit wafer. The resulting unit cell device (i.e., 24 microns) may tightly integrate individual element-level phase control, which may be implemented within large-scale two-dimensional photonic arrays with hemispherical beam steering.

Abstract: A semiconductor-based imaging device and method of manufacture. A direct bond hybridization (DBH) structure is formed on a top surface of a read out integrated circuit (ROIC). A silicon-based detector is bonded to the ROIC via the DBH structure. A non-silicon-based detector is bonded to the DBH structure located on the top of the ROIC using indium-based hybridization.

Abstract: An imaging and asynchronous laser pulse detector (ALPD) device, imaging cell of the imaging and ALPD device and method of use is disclosed. A detector generates an electrical signal in response to receiving an optical signal, wherein a frequency of the electrical signal is indicative of a frequency of the optical signal. A first detection/readout circuit is sensitive to a first frequency range, and a second detection/readout circuit is sensitive to a second frequency range. The first detection/readout circuit allows the electrical signal to pass from the first detection/readout circuit to the second detection/readout circuit.

Abstract: A direct-bond hybridization (DBH) method is provided to assemble a sensor wafer device. The DBH method includes fabricating an optical element on a handle wafer and depositing first oxide with n-x thickness on the optical element where n is an expected final oxide thickness of the sensor wafer, depositing second oxide with x thickness onto a sensor wafer, executing layer transfer of the optical element by a DBH fusion bond technique to the sensor wafer whereby the first and second oxides form an oxide layer of n thickness between the optical element and the sensor wafer and removing the handle wafer.

Abstract: A semiconductor-based imaging device and method of manufacture. A direct bond hybridization (DBH) structure is formed on a top surface of a read out integrated circuit (ROIC). A silicon-based detector is bonded to the ROIC via the DBH structure. A non-silicon-based detector is bonded to the DBH structure located on the top of the ROIC using indium-based hybridization.

Abstract: An electrical device includes a substrate, a dielectric layer supported by the substrate, and an electrically conductive vertical interconnect extending through the dielectric layer. The dielectric layer may be formed at low-temperature below the thermal degradation temperature of thermally-sensitive material in the device. The dielectric layer may be a low-stress layer that imparts no stress or less stress than a failure stress of fragile material in the device. The dielectric layer may be formed during a processing step to planarize the electrical device at that step. The vertical interconnect may be diffusion bondable with another opposing interconnect at a low-temperature below the thermal degradation temperature of thermally-sensitive material in the device. The vertical interconnect may have a coefficient of thermal expansion (CTE) that is greater than a CTE of the dielectric layer to facilitate 3D-integration.

Abstract: Methods and apparatus for an assembly having a first wafer including bulk material and a layer having microelectronics and a wafer with a deposited thin film which is bonded to the first wafer such that the reflected film is embedded within the composed assembly. The reflector wafer can include a handle wafer and a thin film having reflectance characteristics to prevent imaging of the microelectronics via light through the bulk material.

Abstract: Interconnects and methods of fabricating a plurality of interconnects. The method includes depositing a conformal layer of a plating base in each of a plurality of vias, and depositing a photoresist on two portions of a surface of the plating base outside and above the plurality of vias. The method also includes depositing a plating metal over the plating base in each of the plurality of vias, the depositing resulting in each of the plurality of vias being completely filled or incompletely filled, performing a chemical mechanical planarization (CMP), and performing metrology to determine if any of the plurality of vias is incompletely filled following the depositing the plating metal. A second iteration of the depositing the plating metal over the plating base is performed in each of the plurality of vias based on determining that at least one of the plurality of vias is incompletely filled.

Abstract: A focal plane array includes a mosaic integrated circuit device having a plurality of discrete integrated circuit tiles mounted on a motherboard. The focal plane array includes an optically continuous detector array electrically connected to the mosaic integrated circuit device with an interposer disposed therebetween. The interposer is configured to adjust a pitch of the continuous detector array to match a pitch of each of the plurality of discrete integrated circuit tiles so that the optical gaps between each of the plurality of integrated circuit tiles on the motherboard are minimized and the detector array is optically continuous, having high yield over the large format focal plane array.

Abstract: Disclosed herein are interconnects and methods of fabricating a plurality of interconnects. The method includes depositing a conformal layer of a plating base in each of a plurality of vias, and depositing a photoresist on two portions of a surface of the plating base outside and above the plurality of vias. The method also includes depositing a plating metal over the plating base in each of the plurality of vias, the depositing resulting in each of the plurality of vias being completely filled or incompletely filled, performing a chemical mechanical planarization (CMP), and performing metrology to determine if any of the plurality of vias is incompletely filled following the depositing the plating metal. A second iteration of the depositing the plating metal over the plating base is performed in each of the plurality of vias based on determining that at least one of the plurality of vias is incompletely filled.

Abstract: An integrated circuit assembly including a first wafer bonded to a second wafer with an oxide layer, wherein a first surface of the first wafer is bonded to a first surface of the second wafer. The assembly can include a bonding oxide on a second surface of the second wafer, wherein a surface of the bonding oxide is polished. The assembly can further include a shim secured to the bonding oxide on the second surface of the second wafer to reduce bow of the circuit assembly.

Abstract: A direct-bond hybridization (DBH) method is provided to assemble a sensor wafer device. The DBH method includes fabricating an optical element on a handle wafer and depositing first oxide with n-x thickness on the optical element where n is an expected final oxide thickness of the sensor wafer, depositing second oxide with x thickness onto a sensor wafer, executing layer transfer of the optical element by a DBH fusion bond technique to the sensor wafer whereby the first and second oxides form an oxide layer of n thickness between the optical element and the sensor wafer and removing the handle wafer.

Abstract: A semiconductor-based imaging device and method of manufacture. A direct bond hybridization (DBH) structure is formed on a top surface of a read out integrated circuit (ROIC). A silicon-based detector is bonded to the ROIC via the DBH structure. A non-silicon-based detector is bonded to the DBH structure located on the top of the ROIC using indium-based hybridization.

Abstract: Methods and apparatus for an assembly having directly bonded first and second wafers where the assembly includes a backside surface and a front side surface. The first wafer includes IO signal connections vertically routed to the direct bonding interface by a first one of the bonding posts on the first wafer bonded to a first one of the bonding posts on the second wafer. The second wafer includes vertical routing of the IO signal connections from first one though the bonding posts on the second wafer to IO pads on a backside surface of the assembly.

Abstract: An electronic device for interconnection with an integrated circuit device is provided. The electronic device includes an interconnection surface configured to oppose the integrated circuit device with an interconnect structure disposed therebetween. The electronic device also includes at least one electronic device contact pad disposed on the interconnection surface for bonding to the interconnect structure. The at least one electronic device contact pad has at least one 3-dimensional projection configured to extend from the electronic device contact pad toward the integrated circuit device. The at least one 3-dimensional projection is configured to aid in bonding the electronic device contact pad to the interconnect structure to electrically couple the electronic device to the integrated circuit device.

Abstract: Disclosed herein are interconnects and methods of fabricating a plurality of interconnects. The method includes depositing a conformal layer of a plating base in each of a plurality of vias, and depositing a photoresist on two portions of a surface of the plating base outside and above the plurality of vias. The method also includes depositing a plating metal over the plating base in each of the plurality of vias, the depositing resulting in each of the plurality of vias being completely filled or incompletely filled, performing a chemical mechanical planarization (CMP), and performing metrology to determine if any of the plurality of vias is incompletely filled following the depositing the plating metal. A second iteration of the depositing the plating metal over the plating base is performed in each of the plurality of vias based on determining that at least one of the plurality of vias is incompletely filled.