Patents by Inventor Sean P. Kilcoyne
Sean P. Kilcoyne has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 11222813Abstract: A method of manufacturing a wafer assembly includes forming an array of planar wafer level metal posts extending from a surface of a substrate of a first wafer. After forming the array of posts, an oxide layer is applied over the surface of the first wafer and around the array of posts, the oxide layer being applied at a temperature of below 150 degrees Celsius.Type: GrantFiled: November 6, 2019Date of Patent: January 11, 2022Assignee: Raytheon CompanyInventors: Sean P. Kilcoyne, Eric R. Miller, George Grama
-
Publication number: 20210227158Abstract: An imaging and asynchronous laser pulse detector (ALPD) device, imaging cell of the imaging and ALPD device and method of use is disclosed. A detector generates an electrical signal in response to receiving an optical signal, wherein a frequency of the electrical signal is indicative of a frequency of the optical signal. A first detection/readout circuit is sensitive to a first frequency range, and a second detection/readout circuit is sensitive to a second frequency range. The first detection/readout circuit allows the electrical signal to pass from the first detection/readout circuit to the second detection/readout circuit.Type: ApplicationFiled: January 22, 2020Publication date: July 22, 2021Inventors: Adam M. Kennedy, Michael J. Batinica, Scott M. Taylor, Sean P. Kilcoyne, Paul Bryant
-
Publication number: 20210043665Abstract: An integrated circuit assembly including a first wafer bonded to a second wafer with an oxide layer, wherein a first surface of the first wafer is bonded to a first surface of the second wafer. The assembly can include a bonding oxide on a second surface of the second wafer, wherein a surface of the bonding oxide is polished. The assembly can further include a shim secured to the bonding oxide on the second surface of the second wafer to reduce bow of the circuit assembly.Type: ApplicationFiled: October 20, 2020Publication date: February 11, 2021Applicant: Raytheon CompanyInventors: Jeffery H. Burkhart, Sean P. Kilcoyne, Eric Miller
-
Patent number: 10879291Abstract: A three-dimensional (3D) stack is provided and includes a capacitor layer and an integrated circuit (IC) layer. The capacitor layer includes capacitors and capacitor layer connectors respectively communicative with corresponding capacitors. The IC layer is stacked vertically with the capacitor layer and is hybridized to a detector. The IC layer includes IC layer connectors respectively communicative with corresponding capacitor layer connectors.Type: GrantFiled: November 27, 2018Date of Patent: December 29, 2020Assignee: RAYTHEON COMPANYInventors: Neil R. Malone, Sean P. Kilcoyne, Micky Harris
-
Patent number: 10847419Abstract: Disclosed is a process for manufacturing individual die devices, with a desired or predicted amount of flatness, from a bonded wafer process. The flatness of a bonded wafer is measured at point in the wafer manufacturing process. This measurement is compared to a value predetermined by an empirical analysis of previous devices made by the same process. If the flatness of the bonded wafer is not at the predetermined value, then one or more compensation layers are provided to the bonded wafer to obtain the predetermined flatness value. Once obtained, subsequent processing is performed and the resulting individual dies are obtained with the desired flatness characteristic.Type: GrantFiled: March 14, 2018Date of Patent: November 24, 2020Assignee: Raytheon CompanyInventors: Scott S. Miller, Christine Frandsen, Andrew Cahill, Sean P. Kilcoyne, Shannon Wilkey
-
Patent number: 10847569Abstract: Methods and apparatus for proving a sensor assembly. Embodiments can include employing a circuit assembly having a first layer bonded to a second layer with an oxide layer, depositing bonding oxide on the second layer of the circuit assembly, and thinning the first layer of the circuit assembly after depositing the bonding oxide. A coating can be applied over at least a portion of the first layer of the circuit assembly after annealing the circuit assembly. After polishing the bonding oxide on the second surface of the second layer of the circuit assembly, a shim can be secured to the bonding oxide on the second surface of the second layer of the circuit assembly to reduce bow of the assembly. Embodiments can provide a sensor useful in focal plane arrays.Type: GrantFiled: February 26, 2019Date of Patent: November 24, 2020Assignee: Raytheon CompanyInventors: Jeffery H. Burkhart, Sean P. Kilcoyne, Eric Miller
-
Publication number: 20200273893Abstract: Methods and apparatus for proving a sensor assembly. Embodiments can include employing a circuit assembly having a first layer bonded to a second layer with an oxide layer, depositing bonding oxide on the second layer of the circuit assembly, and thinning the first layer of the circuit assembly after depositing the bonding oxide. A coating can be applied over at least a portion of the first layer of the circuit assembly after annealing the circuit assembly. After polishing the bonding oxide on the second surface of the second layer of the circuit assembly, a shim can be secured to the bonding oxide on the second surface of the second layer of the circuit assembly to reduce bow of the assembly. Embodiments can provide a sensor useful in focal plane arrays.Type: ApplicationFiled: February 26, 2019Publication date: August 27, 2020Applicant: Raytheon CompanyInventors: Jeffery H. Burkhart, Sean P. Kilcoyne, Eric Miller
-
Patent number: 10672826Abstract: An imaging system includes a focal plane array comprising a first row of photodetectors, a second row of photodetectors adjacent to the first row of photodetectors, and a segmented isolation grid including portions disposed between photodetectors in the first row of photodetectors and photodetectors in the second row of photodetectors.Type: GrantFiled: April 18, 2018Date of Patent: June 2, 2020Assignee: RAYTHEON COMPANYInventors: Sean P. Kilcoyne, John L. Vampola, George Paloczi
-
Publication number: 20200168651Abstract: A three-dimensional (3D) stack is provided and includes a capacitor layer and an integrated circuit (IC) layer. The capacitor layer includes capacitors and capacitor layer connectors respectively communicative with corresponding capacitors. The IC layer is stacked vertically with the capacitor layer and is hybridized to a detector. The IC layer includes IC layer connectors respectively communicative with corresponding capacitor layer connectors.Type: ApplicationFiled: November 27, 2018Publication date: May 28, 2020Inventors: Neil R. Malone, Sean P. Kilcoyne, Micky Harris
-
Publication number: 20200075396Abstract: A method of manufacturing a wafer assembly includes forming an array of planar wafer level metal posts extending from a surface of a substrate of a first wafer. After forming the array of posts, an oxide layer is applied over the surface of the first wafer and around the array of posts, the oxide layer being applied at a temperature of below 150 degrees Celsius.Type: ApplicationFiled: November 6, 2019Publication date: March 5, 2020Applicant: Raytheon CompanyInventors: Sean P. Kilcoyne, Eric R. Miller, George Grama
-
Patent number: 10515837Abstract: Methods, assemblies, and equipment are described for bonding one or more die that may be of dissimilar thickness to a wafer. The die may be fabricated and singulated with a planarized oxide layer protecting from wafer dicing and handling debris one or more metallized post structures connecting to an integrated circuit. Face sides of the die are bonded to a first handle wafer, such that the respective post structures are aligned in a common plane. The substrate material back sides of the bonded die are then thinned to a uniform thickness and bonded to a second handle wafer. The assembly may then be flipped, and the first handle wafer and protective layer including potential dicing and handling debris removed. The post structures are revealed, resulting in a composite wafer assembly including the second handle and one or more uniformly thinned die mounted thereto.Type: GrantFiled: April 4, 2018Date of Patent: December 24, 2019Assignee: Raytheon CompanyInventors: Sean P. Kilcoyne, Eric R. Miller
-
Patent number: 10504777Abstract: A method of manufacturing an array of planar wafer level metal posts includes plating an array of posts within a photoresist (PR) pattern mold on a substrate of a first wafer. Stripping the PR pattern mold from the substrate and array of posts. Applying an oxide layer, at a temperature of below 150 degrees Celsius, over a surface of the first wafer. Applying chemical-mechanical polishing (CMP) to planarize the oxide layer and the array of posts.Type: GrantFiled: February 13, 2018Date of Patent: December 10, 2019Assignee: Raytheon CompanyInventors: Sean P. Kilcoyne, Eric R. Miller, George Grama
-
Publication number: 20190326346Abstract: An imaging system includes a focal plane array comprising a first row of photodetectors, a second row of photodetectors adjacent to the first row of photodetectors, and a segmented isolation grid including portions disposed between photodetectors in the first row of photodetectors and photodetectors in the second row of photodetectors.Type: ApplicationFiled: April 18, 2018Publication date: October 24, 2019Inventors: Sean P. Kilcoyne, John L. Vampola, George Paloczi
-
Publication number: 20190287854Abstract: Disclosed is a process for manufacturing individual die devices, with a desired or predicted amount of flatness, from a bonded wafer process. The flatness of a bonded wafer is measured at point in the wafer manufacturing process. This measurement is compared to a value predetermined by an empirical analysis of previous devices made by the same process. If the flatness of the bonded wafer is not at the predetermined value, then one or more compensation layers are provided to the bonded wafer to obtain the predetermined flatness value. Once obtained, subsequent processing is performed and the resulting individual dies are obtained with the desired flatness characteristic.Type: ApplicationFiled: March 14, 2018Publication date: September 19, 2019Applicant: RAYTHEON COMPANYInventors: Scott S. Miller, Christine Frandsen, Andrew Cahill, Sean P. Kilcoyne, Shannon Wilkey
-
Patent number: 10418406Abstract: Aspects and examples described herein provide a hybrid imaging sensor chip assembly for reducing undesired radiative transfer between a complementary metal-oxide semiconductor (CMOS) read-out integrated circuit (ROIC) and an optical detector, and methods of manufacturing a hybrid imaging sensor chip assembly. In one example, a hybrid imaging sensor chip assembly includes an optical detector configured to collect electromagnetic radiation incident thereon, a complementary metal-oxide semiconductor (CMOS) read-out integrated circuit (ROIC), and a radiation-shielding wafer interposed between the optical detector and the CMOS ROIC, the radiation-shielding wafer including a plurality of through wafer vias (TWVs) electrically coupled to the optical detector and the CMOS ROIC, the radiation-shielding wafer being positioned to prevent radiative transfer between the CMOS ROIC and the optical detector.Type: GrantFiled: December 28, 2017Date of Patent: September 17, 2019Assignee: RAYTHEON COMPANYInventors: Sean P. Kilcoyne, John L. Vampola, Barry M. Starr, Chad W. Fulk, Christopher L. Mears, John J. Drab
-
Publication number: 20190252244Abstract: A method of manufacturing an array of planar wafer level metal posts includes plating an array of posts within a photoresist (PR) pattern mold on a substrate of a first wafer. Stripping the PR pattern mold from the substrate and array of posts. Applying an oxide layer, at a temperature of below 150 degrees Celsius, over a surface of the first wafer. Applying chemical-mechanical polishing (CMP) to planarize the oxide layer and the array of posts.Type: ApplicationFiled: February 13, 2018Publication date: August 15, 2019Applicant: Raytheon CompanyInventors: Sean P. Kilcoyne, Eric R. Miller, George Grama
-
Publication number: 20190214319Abstract: Systems and methods of in-situ calibration of semiconductor material layer deposition and removal processes are disclosed. Sets of test structures including one or more calibration vias or posts are used to precisely monitor processes such as plating and polishing, respectively. Known (e.g., empirically determined) relationships between the test structure features and product feature enable monitoring of wafer processing progress. Optical inspection of the calibration feature(s) during processing cycles permits dynamic operating condition adjustments and precise cessation of processing when desired product feature characteristics have been achieved.Type: ApplicationFiled: March 18, 2019Publication date: July 11, 2019Applicant: Raytheon CompanyInventors: Sean P. Kilcoyne, Robert M. Emerson, Michael V. Liguori
-
Patent number: 10236226Abstract: Systems and methods of in-situ calibration of semiconductor material layer deposition and removal processes are disclosed. Sets of test structures including one or more calibration vias or posts are used to precisely monitor processes such as plating and polishing, respectively. Known (e.g., empirically determined) relationships between the test structure features and product feature enable monitoring of wafer processing progress. Optical inspection of the calibration feature(s) during processing cycles permits dynamic operating condition adjustments and precise cessation of processing when desired product feature characteristics have been achieved.Type: GrantFiled: March 15, 2016Date of Patent: March 19, 2019Assignee: Raytheon CompanyInventors: Sean P. Kilcoyne, Robert M. Emerson, Michael V. Liguori
-
Publication number: 20180301365Abstract: Methods, assemblies, and equipment are described for bonding one or more die that may be of dissimilar thickness to a wafer. The die may be fabricated and singulated with a planarized oxide layer protecting from wafer dicing and handling debris one or more metallized post structures connecting to an integrated circuit. Face sides of the die are bonded to a first handle wafer, such that the respective post structures are aligned in a common plane. The substrate material back sides of the bonded die are then thinned to a uniform thickness and bonded to a second handle wafer. The assembly may then be flipped, and the first handle wafer and protective layer including potential dicing and handling debris removed. The post structures are revealed, resulting in a composite wafer assembly including the second handle and one or more uniformly thinned die mounted thereto.Type: ApplicationFiled: April 4, 2018Publication date: October 18, 2018Applicant: Raytheon CompanyInventors: Sean P. Kilcoyne, Eric R. Miller
-
Publication number: 20180190705Abstract: Aspects and examples described herein provide a hybrid imaging sensor chip assembly for reducing undesired radiative transfer between a complementary metal-oxide semiconductor (CMOS) read-out integrated circuit (ROIC) and an optical detector, and methods of manufacturing a hybrid imaging sensor chip assembly. In one example, a hybrid imaging sensor chip assembly includes an optical detector configured to collect electromagnetic radiation incident thereon, a complementary metal-oxide semiconductor (CMOS) read-out integrated circuit (ROIC), and a radiation-shielding wafer interposed between the optical detector and the CMOS ROIC, the radiation-shielding wafer including a plurality of through wafer vias (TWVs) electrically coupled to the optical detector and the CMOS ROIC, the radiation-shielding wafer being positioned to prevent radiative transfer between the CMOS ROIC and the optical detector.Type: ApplicationFiled: December 28, 2017Publication date: July 5, 2018Inventors: Sean P. Kilcoyne, John L. Vampola, Barry M. Starr, Chad W. Fulk, Christopher L. Mears, John J. Drab