Patents by Inventor Sean TEEHAN
Sean TEEHAN has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Publication number: 20240088268Abstract: A method and structures are used to fabricate a nanosheet semiconductor device. Nanosheet fins including nanosheet stacks including alternating silicon (Si) layers and silicon germanium (SiGe) layers are formed on a substrate and etched to define a first end and a second end along a first axis between which each nanosheet fin extends parallel to every other nanosheet fin. The SiGe layers are undercut in the nanosheet stacks at the first end and the second end to form divots, and a dielectric is deposited in the divots. The SiGe layers between the Si layers are removed before forming source and drain regions of the nanosheet semiconductor device such that there are gaps between the Si layers of each nanosheet stack, and the dielectric anchors the Si layers. The gaps are filled with an oxide that is removed after removing the dummy gate and prior to forming the replacement gate.Type: ApplicationFiled: April 12, 2023Publication date: March 14, 2024Inventors: Marc A. Bergendahl, Kangguo Cheng, Fee Li Lie, Eric R. Miller, John R. Sporre, Sean Teehan
-
Patent number: 11869936Abstract: A semiconductor device includes a fin structure including a recess formed in an upper surface of the fin structure, an inner gate formed in the recess of the fin structure, and an outer gate formed outside and around the fin structure.Type: GrantFiled: August 14, 2021Date of Patent: January 9, 2024Assignee: International Business Machines CorporationInventors: Marc Adam Bergendahl, Gauri Karve, Fee Li Lie, Eric R. Miller, Robert Russell Robison, John Ryan Sporre, Sean Teehan
-
Patent number: 11869937Abstract: A semiconductor device including a fin structure including a recess, a first gate formed in the recess of the fin structure, and a second gate formed outside the fin structure.Type: GrantFiled: January 19, 2022Date of Patent: January 9, 2024Assignee: International Business Machines CorporationInventors: Marc Adam Bergendahl, Gauri Karve, Fee Li Lie, Eric R. Miller, Robert Russell Robison, John Ryan Sporre, Sean Teehan
-
Publication number: 20230352480Abstract: A method of forming a semiconductor device that includes forming a trench adjacent to a gate structure to expose a contact surface of one of a source region and a drain region. A sacrificial spacer may be formed on a sidewall of the trench and on a sidewall of the gate structure. A metal contact may then be formed in the trench to at least one of the source region and the drain region. The metal contact has a base width that is less than an upper surface width of the metal contact. The sacrificial spacer may be removed, and a substantially conformal dielectric material layer can be formed on sidewalls of the metal contact and the gate structure. Portions of the conformally dielectric material layer contact one another at a pinch off region to form an air gap between the metal contact and the gate structure.Type: ApplicationFiled: December 1, 2022Publication date: November 2, 2023Inventors: Marc A. Bergendahl, Kangguo Cheng, Fee Li Lie, Eric R. Miller, John R. Sporre, Sean Teehan
-
Patent number: 11673766Abstract: Systems, computer-implemented methods, and computer program products that can facilitate elevator analytics and/or elevator optimization components are provided. According to an embodiment, a system can comprise a memory that stores computer executable components and a processor that executes the computer executable components stored in the memory. The computer executable components can comprise a prediction component that can predict a current destination of an elevator passenger based on historical elevator usage data of the elevator passenger. The computer executable components can further comprise an assignment component that can assign the elevator passenger to an elevator based on the current destination.Type: GrantFiled: October 29, 2018Date of Patent: June 13, 2023Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Gauri Karve, Tara Astigarraga, Eric Miller, Kangguo Cheng, Fee Li Lie, Sean Teehan, Marc Bergendahl
-
Publication number: 20230171114Abstract: A physical unclonable function (PUF) device includes a ring oscillator, a plurality of band-pass filters, a demultiplexer, and a latch. The ring oscillator generates a frequency signal. Each passive band-pass filter performs filtering on the frequency signal to pass the frequency signal or block the frequency signal. The demultiplexer receives a set of challenge bits and delivers the frequency signal to a selected passive band-pass filter among the plurality of passive band-passed filters based on the challenge bit. The latch outputs a response bit in response to the filtering performed by the selected passive band-pass filter.Type: ApplicationFiled: November 30, 2021Publication date: June 1, 2023Inventors: Dallas Lea, Yann Mignot, Marc A. Bergendahl, Alex Joseph Varghese, Sean Teehan, Andrew M. Greene, Matthew T. Shoudy
-
Patent number: 11652161Abstract: A method and structures are used to fabricate a nanosheet semiconductor device. Nanosheet fins including nanosheet stacks including alternating silicon (Si) layers and silicon germanium (SiGe) layers are formed on a substrate and etched to define a first end and a second end along a first axis between which each nanosheet fin extends parallel to every other nanosheet fin. The SiGe layers are undercut in the nanosheet stacks at the first end and the second end to form divots, and a dielectric is deposited in the divots. The SiGe layers between the Si layers are removed before forming source and drain regions of the nanosheet semiconductor device such that there are gaps between the Si layers of each nanosheet stack, and the dielectric anchors the Si layers. The gaps are filled with an oxide that is removed after removing the dummy gate and prior to forming the replacement gate.Type: GrantFiled: June 11, 2021Date of Patent: May 16, 2023Assignee: Tessera LLCInventors: Marc A. Bergendahl, Kangguo Cheng, Fee Li Lie, Eric R. Miller, John R. Sporre, Sean Teehan
-
Patent number: 11646235Abstract: Embodiments of the present invention are directed to fabrication method and resulting structures for vertical tunneling field effect transistors (VFETs) having a dual liner bottom spacer. In a non-limiting embodiment of the invention, a first liner is formed on a top surface of a source or drain (S/D) region and sidewalls of a semiconductor fin. Portions of a spacer are removed to expose a first region and a second region of the first liner. The first region of the first liner is directly on the S/D region and the second region is over the semiconductor fin. A second liner is formed on the first liner. A first portion of the second liner is formed by selectively depositing dielectric material on the exposed first region and exposed second region of the first liner. The first liner and the second liner collectively define the dual liner bottom spacer.Type: GrantFiled: July 22, 2021Date of Patent: May 9, 2023Assignee: International Business Machines CorporationInventors: Eric Miller, Marc A. Bergendahl, Kangguo Cheng, Sean Teehan, John Sporre
-
Patent number: 11557589Abstract: A method of forming a semiconductor device that includes forming a trench adjacent to a gate structure to expose a contact surface of one of a source region and a drain region. A sacrificial spacer may be formed on a sidewall of the trench and on a sidewall of the gate structure. A metal contact may then be formed in the trench to at least one of the source region and the drain region. The metal contact has a base width that is less than an upper surface width of the metal contact. The sacrificial spacer may be removed, and a substantially conformal dielectric material layer can be formed on sidewalls of the metal contact and the gate structure. Portions of the conformally dielectric material layer contact one another at a pinch off region to form an air gap between the metal contact and the gate structure.Type: GrantFiled: March 30, 2020Date of Patent: January 17, 2023Assignee: Tessera, LLCInventors: Marc A. Bergendahl, Kangguo Cheng, Fee Li Lie, Eric R. Miller, John R. Sporre, Sean Teehan
-
Publication number: 20220140074Abstract: A semiconductor device including a fin structure including a recess, a first gate formed in the recess of the fin structure, and a second gate formed outside the fin structure.Type: ApplicationFiled: January 19, 2022Publication date: May 5, 2022Inventors: Marc Adam Bergendahl, Gauri Karve, Fee Li Lie, Eric R. Miller, Robert Russell Robison, John Ryan Sporre, Sean Teehan
-
Patent number: 11239316Abstract: A semiconductor device includes a fin structure including a cylindrical shape, an inner gate formed inside the fin structure, and an outer gate formed outside the fin structure and connected to the inner gate.Type: GrantFiled: April 30, 2019Date of Patent: February 1, 2022Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Marc Adam Bergendahl, Gauri Karve, Fee Li Lie, Eric R. Miller, Robert Russell Robison, John Ryan Sporre, Sean Teehan
-
Publication number: 20210376078Abstract: A semiconductor device includes a fin structure including a recess formed in an upper surface of the fin structure, an inner gate formed in the recess of the fin structure, and an outer gate formed outside and around the fin structure.Type: ApplicationFiled: August 14, 2021Publication date: December 2, 2021Inventors: Marc Adam BERGENDAHL, Gauri KARVE, Fee Li LIE, Eric R. MILLER, Robert Russell ROBISON, John Ryan SPORRE, Sean TEEHAN
-
Publication number: 20210351082Abstract: Embodiments of the present invention are directed to fabrication method and resulting structures for vertical tunneling field effect transistors (VFETs) having a dual liner bottom spacer. In a non-limiting embodiment of the invention, a first liner is formed on a top surface of a source or drain (S/D) region and sidewalls of a semiconductor fin. Portions of a spacer are removed to expose a first region and a second region of the first liner. The first region of the first liner is directly on the S/D region and the second region is over the semiconductor fin. A second liner is formed on the first liner. A first portion of the second liner is formed by selectively depositing dielectric material on the exposed first region and exposed second region of the first liner. The first liner and the second liner collectively define the dual liner bottom spacer.Type: ApplicationFiled: July 22, 2021Publication date: November 11, 2021Inventors: Eric Miller, Marc A. Bergendahl, Kangguo Cheng, Sean Teehan, John Sporre
-
Patent number: 11152252Abstract: An interconnect structure and methods of forming the interconnect structure an interconnect dielectric including at least one contact landing within the interconnect dielectric and/or underlying the interconnect dielectric. The structure and methods include roughening an exposed surface of at least one contact landing to increase the surface area of a conductive metal subsequently disposed in a contact feature and in direct contact with the roughened surface of the least one contact landing.Type: GrantFiled: November 5, 2019Date of Patent: October 19, 2021Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Kangguo Cheng, Sean Teehan, Alex J. Varghese
-
Patent number: 11152266Abstract: Embodiments of the present invention are directed to fabrication method and resulting structures for vertical tunneling field effect transistors (VFETs) having a dual liner bottom spacer. In a non-limiting embodiment of the invention, a first liner is formed on a top surface of a source or drain (S/D) region and sidewalls of a semiconductor fin. Portions of a spacer are removed to expose a first region and a second region of the first liner. The first region of the first liner is directly on the S/D region and the second region is over the semiconductor fin. A second liner is formed on the first liner. A first portion of the second liner is formed by selectively depositing dielectric material on the exposed first region and exposed second region of the first liner. The first liner and the second liner collectively define the dual liner bottom spacer.Type: GrantFiled: October 2, 2019Date of Patent: October 19, 2021Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Eric Miller, Marc A. Bergendahl, Kangguo Cheng, Sean Teehan, John Sporre
-
Publication number: 20210305405Abstract: A method and structures are used to fabricate a nanosheet semiconductor device. Nanosheet fins including nanosheet stacks including alternating silicon (Si) layers and silicon germanium (SiGe) layers are formed on a substrate and etched to define a first end and a second end along a first axis between which each nanosheet fin extends parallel to every other nanosheet fin. The SiGe layers are undercut in the nanosheet stacks at the first end and the second end to form divots, and a dielectric is deposited in the divots. The SiGe layers between the Si layers are removed before forming source and drain regions of the nanosheet semiconductor device such that there are gaps between the Si layers of each nanosheet stack, and the dielectric anchors the Si layers. The gaps are filled with an oxide that is removed after removing the dummy gate and prior to forming the replacement gate.Type: ApplicationFiled: June 11, 2021Publication date: September 30, 2021Inventors: Marc A. Bergendahl, Kangguo Cheng, Fee Li Lie, Eric R. Miller, John R. Spoore, Sean Teehan
-
Patent number: 11127815Abstract: A semiconductor device includes a fin structure having a circular cylindrical shape, and including a first recess formed on a first side of the fin structure and a second recess formed on a second side of the fin structure opposite the first side, an inner gate formed inside the fin structure, and an inner gate insulating layer formed between the inner gate and an inner surface of the fin structure.Type: GrantFiled: April 30, 2019Date of Patent: September 21, 2021Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Marc Adam Bergendahl, Gauri Karve, Fee Li Lie, Eric R. Miller, Robert Russell Robison, John Ryan Sporre, Sean Teehan
-
Patent number: 11075299Abstract: Embodiments of the invention are directed to a method that includes forming a fin over a major surface of a substrate. The fin includes an active fin region having a top fin surface and a fin sidewall. The top fin surface is substantially parallel with respect to the major surface, and the fin sidewall is substantially perpendicular with respect to the major surface. A gate is formed over and around a central portion of the fin, the gate having a bottom gate region and a top gate region. The bottom gate region is substantially below the top fin surface and includes a bottom gate region sidewall that is substantially parallel with respect to the fin sidewall. The top gate region is substantially above the top fin surface and includes a top gate region sidewall that is at an angle with respect to the major surface.Type: GrantFiled: July 1, 2019Date of Patent: July 27, 2021Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Eric Miller, Gauri Karve, Marc A. Bergendahl, Fee Li Lie, Kangguo Cheng, Sean Teehan
-
Patent number: 11043581Abstract: A method and structures are used to fabricate a nanosheet semiconductor device. Nanosheet fins including nanosheet stacks including alternating silicon (Si) layers and silicon germanium (SiGe) layers are formed on a substrate and etched to define a first end and a second end along a first axis between which each nanosheet fin extends parallel to every other nanosheet fin. The SiGe layers are undercut in the nanosheet stacks at the first end and the second end to form divots, and a dielectric is deposited in the divots. The SiGe layers between the Si layers are removed before forming source and drain regions of the nanosheet semiconductor device such that there are gaps between the Si layers of each nanosheet stack, and the dielectric anchors the Si layers. The gaps are filled with an oxide that is removed after removing the dummy gate and prior to forming the replacement gate.Type: GrantFiled: February 21, 2020Date of Patent: June 22, 2021Assignee: Tessera, Inc.Inventors: Marc A. Bergendahl, Kangguo Cheng, Fee Li Lie, Eric R. Miller, John R. Sporre, Sean Teehan
-
Publication number: 20210104440Abstract: Embodiments of the present invention are directed to fabrication method and resulting structures for vertical tunneling field effect transistors (VFETs) having a dual liner bottom spacer. In a non-limiting embodiment of the invention, a first liner is formed on a top surface of a source or drain (S/D) region and sidewalls of a semiconductor fin. Portions of a spacer are removed to expose a first region and a second region of the first liner. The first region of the first liner is directly on the S/D region and the second region is over the semiconductor fin. A second liner is formed on the first liner. A first portion of the second liner is formed by selectively depositing dielectric material on the exposed first region and exposed second region of the first liner. The first liner and the second liner collectively define the dual liner bottom spacer.Type: ApplicationFiled: October 2, 2019Publication date: April 8, 2021Inventors: ERIC MILLER, Marc A. Bergendahl, Kangguo Cheng, Sean Teehan, John Sporre