Abstract: A semiconductor device comprises a nanowire arranged over a substrate, a gate stack arranged around the nanowire, a spacer arranged along a sidewall of the gate stack, a cavity defined by a distal end of the nanowire and the spacer, and a source/drain region partially disposed in the cavity and in contact with the distal end of the nanowire.

Abstract: A semiconductor device includes a fin structure including a cylindrical shape, an inner gate formed inside the fin structure, and an outer gate formed outside the fin structure and connected to the inner gate.

Abstract: A semiconductor device includes a fin structure having a circular cylindrical shape, and including a first recess formed on a first side of the fin structure and a second recess formed on a second side of the fin structure opposite the first side, an inner gate formed inside the fin structure, and an inner gate insulating layer formed between the inner gate and an inner surface of the fin structure.

Abstract: A semiconductor device includes a fin structure including a cylindrical shape, an inner gate formed inside the fin structure, and an outer gate formed outside the fin structure and connected to the inner gate.

Abstract: A method for fabricating a semiconductor structure includes forming a plurality of mandrel structures. A plurality of first spacers is formed on sidewalls of the mandrel structures. A plurality of second spacers is formed on sidewalls of the first spacers. The plurality of first spacers is removed selective to the plurality of second spacers and mandrel structures. A cut mask is formed over a first set of second spacers of the plurality of second spacers and a first set of mandrel structures of the plurality of mandrel structures. A second set of second spacers of the plurality of spacers and a second set of mandrel structures of the plurality of mandrel structures remain exposed. One of the second set of mandrel structures and the second set of second spacers is removed selective to the second set of second spacers and the second set of mandrel structures, respectively.

Abstract: Techniques relate to a gate stack for a semiconductor device. A vertical fin is formed on a substrate. The vertical fin has an upper portion and a bottom portion. The upper portion of the vertical fin has a recessed portion on sides of the upper portion. A gate stack is formed in the recessed portion of the upper portion of the vertical fin.

Abstract: A semiconductor device comprises a nanowire arranged over a substrate, a gate stack arranged around the nanowire, a spacer arranged along a sidewall of the gate stack, a cavity defined by a distal end of the nanowire and the spacer, and a source/drain region partially disposed in the cavity and in contact with the distal end of the nanowire.

Abstract: A nano-sheet semiconductor structure and a method for fabricating the same. The nano-sheet structure includes a substrate and at least one alternating stack of semiconductor material layers and metal gate material layers. The nano-sheet semiconductor structure further comprises a source region and a drain region. A first plurality of epitaxially grown interconnects contacts the source region and the semiconductor layers in the alternating stack. A second plurality of epitaxially grown interconnects contacts the drain region and the semiconductor layers in the alternating stack. The method includes removing a portion of alternating semiconductor layers and metal gate material layers. A first plurality of interconnects is epitaxially grown between and in contact with the semiconductor layers and the source region. A second plurality of interconnects is epitaxially grown between and in contact with the semiconductor layers and the drain region.

Abstract: A method and structures are used to fabricate a nanosheet semiconductor device. Nanosheet fins including nanosheet stacks including alternating silicon (Si) layers and silicon germanium (SiGe) layers are formed on a substrate and etched to define a first end and a second end along a first axis between which each nanosheet fin extends parallel to every other nanosheet fin. The SiGe layers are undercut in the nanosheet stacks at the first end and the second end to form divots, and a dielectric is deposited in the divots. The SiGe layers between the Si layers are removed before forming source and drain regions of the nanosheet semiconductor device such that there are gaps between the Si layers of each nanosheet stack, and the dielectric anchors the Si layers. The gaps are filled with an oxide that is removed after removing the dummy gate and prior to forming the replacement gate.

Abstract: Methods are provided to implement a cyclic etch process to remove oxide layers for semiconductor device fabrication. For example, a method comprises performing a cyclic etch process to incrementally etch an oxide layer, wherein the cyclic etch process comprises sequentially performing at least two instances of an etch cycle. The etch cycle comprises performing an etch process to partially etch a portion of the oxide layer using an etch chemistry and environment which is configured to etch down the oxide layer at an etch rate of about 25 angstroms/minute or less, and performing a thermal treatment to remove by-products of the etch process. The cyclic etch process can be implemented as part of a replacement metal gate process to remove a dummy gate oxide layer of a dummy gate structure as part of, e.g., a FinFET semiconductor fabrication process flow.

Abstract: Methods of forming semiconductor fins include forming first spacers on a first sidewall of each of a plurality of mandrels using a directional deposition process. A finless region is masked by forming a mask on a second sidewall of one or more of the plurality of mandrels. Second spacers are formed on a second sidewall of unmasked mandrels using a directional deposition process. The finless region is unmasked and each of the plurality of mandrels is etched away. Fins are formed from a substrate using the first and second spacers as a mask, such that no fins are formed in the finless region.

Abstract: Methods of forming semiconductor fins include forming first spacers on a first sidewall of each of multiple mandrels using an angled deposition process. A second sidewall of one or more of the mandrels is masked in a finless region. Second spacers are formed on a second sidewall of all unmasked mandrels. Semiconductor fins are formed from a substrate using the first and second spacers as a pattern mask.

Abstract: Transistors and methods of forming the same include forming a semiconductor fin from a first material on dielectric layer. Material is etched away from the dielectric layer directly underneath a channel region of the semiconductor fin, with the semiconductor fin still being supported by the dielectric layer in a source and drain region. A gate stack is formed around the channel region of the semiconductor fin, with a portion of the gate stack underneath the semiconductor fin being larger than a portion of the gate stack above the semiconductor fin.

Abstract: A method and structures are used to fabricate a nanosheet semiconductor device. Nanosheet fins including nanosheet stacks including alternating silicon (Si) layers and silicon germanium (SiGe) layers are formed on a substrate and etched to define a first end and a second end along a first axis between which each nanosheet fin extends parallel to every other nanosheet fin. The SiGe layers are undercut in the nanosheet stacks at the first end and the second end to form divots, and a dielectric is deposited in the divots. The SiGe layers between the Si layers are removed before forming source and drain regions of the nanosheet semiconductor device such that there are gaps between the Si layers of each nanosheet stack, and the dielectric anchors the Si layers. The gaps are filled with an oxide that is removed after removing the dummy gate and prior to forming the replacement gate.

Abstract: Methods are provided to implement a cyclic etch process to remove oxide layers for semiconductor device fabrication. For example, a method comprises performing a cyclic etch process to incrementally etch an oxide layer, wherein the cyclic etch process comprises sequentially performing at least two instances of an etch cycle. The etch cycle comprises performing an etch process to partially etch a portion of the oxide layer using an etch chemistry and environment which is configured to etch down the oxide layer at an etch rate of about 25 angstroms/minute or less, and performing a thermal treatment to remove by-products of the etch process. The cyclic etch process can be implemented as part of a replacement metal gate process to remove a dummy gate oxide layer of a dummy gate structure as part of, e.g., a FinFET semiconductor fabrication process flow.

Abstract: A method of forming a complementary metal oxide semiconductor (CMOS) device on a substrate, including forming a plurality of vertical fins on the substrate, forming a first set of source/drain projections on the first subset of vertical fins, forming a second set of source/drain projections on the second subset of vertical fins, where the second set of source/drain projections is a different oxidizable material from the oxidizable material of the first set of source/drain projections, converting a portion of each of the second set of source/drain projections and a portion of each of the first set of source/drain projections to an oxide, removing the converted oxide portion of the first set of source/drain projections to form a source/drain seed mandrel, and removing a portion of the converted oxide portion of the second set of source/drain projections to form a dummy post.

Abstract: Embodiments are directed to methods and resulting structures for a vertical field effect transistor (VFET) having a super long channel. A pair of semiconductor fins is formed on a substrate. A semiconductor pillar is formed between the semiconductor fins on the substrate. A region that extends under all of the semiconductor fins and under part of the semiconductor pillar is doped. A conductive gate is formed over a channel region of the semiconductor fins and the semiconductor pillar. A surface of the semiconductor pillar serves as an extended channel region when the gate is active.

Abstract: Embodiments are directed to methods and resulting structures for a vertical field effect transistor (VFET) having a super long channel. A pair of semiconductor fins is formed on a substrate. A semiconductor pillar is formed between the semiconductor fins on the substrate. A region that extends under all of the semiconductor fins and under part of the semiconductor pillar is doped. A conductive gate is formed over a channel region of the semiconductor fins and the semiconductor pillar. A surface of the semiconductor pillar serves as an extended channel region when the gate is active.

Abstract: A method for manufacturing a semiconductor device includes forming a first semiconductor layer on a substrate having a {100} crystallographic surface orientation, forming a second semiconductor layer on the substrate, patterning the first semiconductor layer and the second semiconductor layer into a first plurality of fins and a second plurality of fins, respectively, wherein the first and second plurality of fins extend vertically with respect to the substrate, covering the first plurality of fins and a portion of the substrate corresponding to the first plurality of fins, and epitaxially growing semiconductor layers on exposed portions of the second plurality of fins and on exposed portions of the substrate, wherein the epitaxially grown semiconductor layers on the exposed portions of the second plurality of fins increase a critical dimension of each of the second plurality of fins.

Abstract: A nano-sheet semiconductor structure and a method for fabricating the same. The nano-sheet structure includes a substrate and at least one alternating stack of semiconductor material layers and metal gate material layers. The nano-sheet semiconductor structure further comprises a source region and a drain region. A first plurality of epitaxially grown interconnects contacts the source region and the semiconductor layers in the alternating stack. A second plurality of epitaxially grown interconnects contacts the drain region and the semiconductor layers in the alternating stack. The method includes removing a portion of alternating semiconductor layers and metal gate material layers. A first plurality of interconnects is epitaxially grown between and in contact with the semiconductor layers and the source region. A second plurality of interconnects is epitaxially grown between and in contact with the semiconductor layers and the drain region.