Patents by Inventor Sebastian Schoenberg

Sebastian Schoenberg has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20190141568
    Abstract: System and techniques for publisher control in an information centric network (ICN) are described herein. Named data criteria to identify data for a workload may be constructed. A discriminator for potential publishers of the data may be constructed. An interest packet may be transmitted based on the named data criteria and the discriminator and a response to the interest packet received from one of the potential publishers.
    Type: Application
    Filed: December 28, 2018
    Publication date: May 9, 2019
    Inventors: Ravikumar Balakrishnan, Venkatesan Nallampatti Ekambaram, Srikathyayani Srikanteswara, Jessica C. McCarthy, Eve M. Schooler, Sebastian Schoenberg, Rath Vannithamby, Moreno Ambrosin, Maruti Gupta Hyde
  • Patent number: 10223149
    Abstract: A processor includes an interface coupled to a programmable integrated circuit (IC) and a processor core coupled to the interface and to execute a virtual machine monitor (VMM). The VMM provides a virtual device for a virtual machine (VM). The virtual device emulates a hardware interface of a hardware device, wherein the processor core is further to execute the VM to transmit a command through the interface to the programmable IC to update a device model, stored in the programmable IC, for the virtual device.
    Type: Grant
    Filed: December 15, 2016
    Date of Patent: March 5, 2019
    Assignee: Intel Corporation
    Inventor: Sebastian Schoenberg
  • Patent number: 10180911
    Abstract: A processor including logic to execute an instruction to synchronize a mapping from a physical address of a guest of a virtualization based system (guest physical address) to a physical address of the host of the virtualization based system (host physical address), and stored in a translation lookaside buffer (TLB), with a corresponding mapping stored in an extended paging table (EPT) of the virtualization based system.
    Type: Grant
    Filed: June 12, 2017
    Date of Patent: January 15, 2019
    Assignee: Intel Corporation
    Inventors: Steven M. Bennett, Andrew V. Anderson, Gilbert Neiger, Richard Uhlig, Scott Dion Rodgers, Rajesh M. Sankaran, Camron Rust, Sebastian Schoenberg
  • Publication number: 20180196758
    Abstract: A processor including logic to execute an instruction to synchronize a mapping from a physical address of a guest of a virtualization based system (guest physical address) to a physical address of the host of the virtualization based system (host physical address), and stored in a translation lookaside buffer (TLB), with a corresponding mapping stored in an extended paging table (EPT) of the virtualization based system.
    Type: Application
    Filed: March 5, 2018
    Publication date: July 12, 2018
    Inventors: Steven M. Bennett, Andrew V. Anderson, Gilbert Neiger, Richard Uhlig, Scott Dion Rodgers, Rajesh M. Sankaran, Camron Rust, Sebastian Schoenberg
  • Publication number: 20180196759
    Abstract: A processor including logic to execute an instruction to synchronize a mapping from a physical address of a guest of a virtualization based system (guest physical address) to a physical address of the host of the virtualization based system (host physical address), and stored in a translation lookaside buffer (TLB), with a corresponding mapping stored in an extended paging table (EPT) of the virtualization based system.
    Type: Application
    Filed: March 5, 2018
    Publication date: July 12, 2018
    Inventors: Steven M. Bennett, Andrew V. Anderson, Gilbert Neiger, Richard Uhlig, Scott Dion Rodgers, Rajesh M. Sankaran, Camron Rust, Sebastian Schoenberg
  • Publication number: 20180173548
    Abstract: A processor includes an interface coupled to a programmable integrated circuit (IC) and a processor core coupled to the interface and to execute a virtual machine monitor (VMM). The VMM provides a virtual device for a virtual machine (VM). The virtual device emulates a hardware interface of a hardware device, wherein the processor core is further to execute the VM to transmit a command through the interface to the programmable IC to update a device model, stored in the programmable IC, for the virtual device.
    Type: Application
    Filed: December 15, 2016
    Publication date: June 21, 2018
    Inventor: Sebastian Schoenberg
  • Publication number: 20180146071
    Abstract: Generally discussed herein are systems, devices, and methods for interfacing between a host-oriented network (HON) and an information-centric network (ICN). A device can include a first interface to couple to a host-oriented network (HON), a second interface to couple to an information-centric network (ICN), a memory including data stored thereon mapping named data in the ICN to a respective host in the HON, and content processing circuitry to receive an interest packet or content packet from the ICN through the first interface, produce a corresponding HON packet based on the mapping in the memory, and provide the HON packet to the HON through the second interface.
    Type: Application
    Filed: June 29, 2017
    Publication date: May 24, 2018
    Inventors: Nageen Himayat, Srikathyayani Srikanteswara, Christian Maciocco, Hassnaa Moustafa, Eve M. Schooler, Andrew Stephen Brown, Rath Vannithamby, Sebastian Schoenberg
  • Publication number: 20180145907
    Abstract: Generally discussed herein are systems, devices, and methods for routing interests and/or content in an information centric network. A router can include a memory and routing circuitry coupled to the memory, the routing circuitry configured to receive a packet, receive one or more attributes including at least one of (1) a network attribute, (2) a platform attribute, and (3) a content attribute, determine which neighbor node is to receive the packet next based on the received one or more attributes, and forward the packet to the determined neighbor node.
    Type: Application
    Filed: January 24, 2017
    Publication date: May 24, 2018
    Inventors: Rath Vannithamby, Ren Wang, Nageen Himayat, Eve M. Schooler, Vallabhajosyula S. Somayazulu, Christian Maciocco, Srikathyayani Srikanteswara, David John Zage, Sebastian Schoenberg, Andrew Stephen Brown, Maruti Gupta Hyde, Jessica C. McCarthy
  • Publication number: 20180146059
    Abstract: Generally discussed herein are systems, devices, and methods for populating a cache in an information-centric network. A device of an ICN can include a content store including published content and attributes of the published content stored thereon, the attributes including at least two of a device from which the content originated attribute, a lineage attribute, and a service level agreement attribute, and content processing circuitry coupled to the content store, the content processing circuitry configured to manage the published content based on the attributes.
    Type: Application
    Filed: January 24, 2017
    Publication date: May 24, 2018
    Inventors: Sebastian Schoenberg, Andrew Stephen Brown, Srikathyayani Srikanteswara, Jessica C. McCarthy, Eve M. Schooler, Christian Maciocco, Hassnaa Moustafa, Nageen Himayat, Rath Vannithamby, David John Zage
  • Publication number: 20180060247
    Abstract: A processor including logic to execute an instruction to synchronize a mapping from a physical address of a guest of a virtualization based system (guest physical address) to a physical address of the host of the virtualization based system (host physical address), and stored in a translation lookaside buffer (TLB), with a corresponding mapping stored in an extended paging table (EPT) of the virtualization based system.
    Type: Application
    Filed: June 12, 2017
    Publication date: March 1, 2018
    Inventors: Steven M. Bennett, Andrew V. Anderson, Gilbert Neiger, Richard Uhlig, Scott Dion Rodgers, Rajesh M. Sankaran, Camron Rust, Sebastian Schoenberg
  • Patent number: 9678890
    Abstract: A processor including logic to execute an instruction to synchronize a mapping from a physical address of a guest of a virtualization based system (guest physical address) to a physical address of the host of the virtualization based system (host physical address), and stored in a translation lookaside buffer (TLB), with a corresponding mapping stored in an extended paging table (EPT) of the virtualization based system.
    Type: Grant
    Filed: September 28, 2015
    Date of Patent: June 13, 2017
    Assignee: Intel Corporation
    Inventors: Steven M. Bennett, Andrew V. Anderson, Gilbert Neiger, Richard A Uhlig, Scott Dion Rodgers, Rajesh M. Sankaran, Camron Rust, Sebastian Schoenberg
  • Publication number: 20160357886
    Abstract: This disclosure is directed to a system for analytic model development. In general, an analytic system may be able to formulate a model of a target system based on user interaction and data received from the system, and to perform real time activities based on the model. An analytics system may comprise at least a segment recipe module (SRM), a user interface module (UIM) and an automated analytics module (AAM). The SRM may include at least one segment recipe for use in configuring the UIM and AAM. For example, the UIM may be configured to present plain language prompts to a user. At least one of the segment recipe or data input by the user in response to the prompts may be used to configure the AAM to generate the model. The AAM may also perform real time activities that generate notifications, etc. based on the model.
    Type: Application
    Filed: June 4, 2015
    Publication date: December 8, 2016
    Applicant: Intel Corporation
    Inventors: CELESTE FRALICK, RITA CHATTOPADHYAY, SEBASTIAN SCHOENBERG, DONALD SCOTT WILDE, PHILLIP GURBACKI
  • Patent number: 9442868
    Abstract: Embodiments of apparatuses, methods, and systems for delivering an interrupt to a virtual processor are disclosed. In one embodiment, an apparatus includes an interface to receive an interrupt request, delivery logic, and exit logic. The delivery logic is to determine, based on an attribute of the interrupt request, whether the interrupt request is to be delivered to the virtual processor. The exit logic is to transfer control to a host if the delivery logic determines that the interrupt request is not to be delivered to the virtual processor.
    Type: Grant
    Filed: December 10, 2014
    Date of Patent: September 13, 2016
    Assignee: Intel Corporation
    Inventors: Gilbert Neiger, Rajesh Sankaran Madukkarumukumana, Richard A. Uhlig, Udo Steinberg, Sebastian Schoenberg, Sridhar Muthrasanallur, Steven M. Bennett, Andrew V. Anderson, Erik C. Cota-Robles
  • Patent number: 9396000
    Abstract: Methods and systems to permit multiple virtual machines (VMs) to separately configure and access a physical resource, substantially outside of a virtual machine monitor (VMM) that hosts the VMs. Each of a plurality of virtual machines (VMs) may access and configure the physical device through corresponding instances of a device driver that exposes controllable functions of the physical device within the VMs. VM-specific configuration parameters and connection information may be maintained for each of the VMs, outside of a VMM, to reconfigure or virtualize the physical device for each of the VMs with the corresponding VM-specific configuration parameters and connection information. Physical device virtualization augmentation features may be implemented within a combination of a physical device controller and a host device driver that executes outside of the VM.
    Type: Grant
    Filed: December 25, 2010
    Date of Patent: July 19, 2016
    Assignee: Intel Corporation
    Inventors: Xue Yang, Hsin-Yuo Liu, Praveen Gopalakrishnan, Sebastian Schoenberg, Sanjay Kumar
  • Patent number: 9372806
    Abstract: A processor including logic to execute an instruction to synchronize a mapping from a physical address of a guest of a virtualization based system (guest physical address) to a physical address of the host of the virtualization based system (host physical address), and stored in a translation lookaside buffer (TLB), with a corresponding mapping stored in an extended paging table (EPT) of the virtualization based system.
    Type: Grant
    Filed: September 28, 2015
    Date of Patent: June 21, 2016
    Assignee: Intel Corporation
    Inventors: Steven M. Bennett, Andrew V. Anderson, Gilbert Neiger, Richard A Uhlig, Scott Dion Rodgers, Rajesh M. Sankaran, Camron Rust, Sebastian Schoenberg
  • Patent number: 9372807
    Abstract: A processor including logic to execute an instruction to synchronize a mapping from a physical address of a guest of a virtualization based system (guest physical address) to a physical address of the host of the virtualization based system (host physical address), and stored in a translation lookaside buffer (TLB), with a corresponding mapping stored in an extended paging table (EPT) of the virtualization based system.
    Type: Grant
    Filed: September 28, 2015
    Date of Patent: June 21, 2016
    Assignee: Intel Corporation
    Inventors: Steven M. Bennett, Andrew V. Anderson, Gilbert Neiger, Richard Uhlig, Scott Dion Rodgers, Rajesh M. Sankaran, Camron Rust, Sebastian Schoenberg
  • Patent number: 9330021
    Abstract: A processor including logic to execute an instruction to synchronize a mapping from a physical address of a guest of a virtualization based system (guest physical address) to a physical address of the host of the virtualization based system (host physical address), and stored in a translation lookaside buffer (TLB), with a corresponding mapping stored in an extended paging table (EPT) of the virtualization based system.
    Type: Grant
    Filed: September 28, 2015
    Date of Patent: May 3, 2016
    Assignee: Intel Corporation
    Inventors: Steven M. Bennett, Andrew V. Anderson, Gilbert Neiger, Richard A Uhlig, Scott Dion Rodgers, Rajesh M. Sankaran, Camron Rust, Sebastian Schoenberg
  • Patent number: 9317441
    Abstract: Embodiments of systems, apparatuses, and methods for performing guest logical memory address to host physical memory address translation are described. In some embodiments, a system receives the guest logical memory address and determines an index page reference from the guest logical memory address. The system further retrieves a page index corresponding to the virtual machine. In addition, the system retrieves a first part of the host physical memory address from index page using the page index and a second part of the host physical memory address from the guest logical memory address. The system generates the host physical memory address from the first and second parts of the host physical memory address.
    Type: Grant
    Filed: December 22, 2011
    Date of Patent: April 19, 2016
    Assignee: Intel Cororation
    Inventor: Sebastian Schoenberg
  • Patent number: 9298640
    Abstract: A processor including logic to execute an instruction to synchronize a mapping from a physical address of a guest of a virtualization based system (guest physical address) to a physical address of the host of the virtualization based system (host physical address), and stored in a translation lookaside buffer (TLB), with a corresponding mapping stored in an extended paging table (EPT) of the virtualization based system.
    Type: Grant
    Filed: September 28, 2015
    Date of Patent: March 29, 2016
    Assignee: Intel Corporation
    Inventors: Steven M. Bennett, Andrew V. Anderson, Gilbert Neiger, Richard A Uhlig, Scott Dion Rodgers, Rajesh M. Sankaran, Camron Rust, Sebastian Schoenberg
  • Patent number: 9298641
    Abstract: A processor including logic to execute an instruction to synchronize a mapping from a physical address of a guest of a virtualization based system (guest physical address) to a physical address of the host of the virtualization based system (host physical address), and stored in a translation lookaside buffer (TLB), with a corresponding mapping stored in an extended paging table (EPT) of the virtualization based system.
    Type: Grant
    Filed: September 28, 2015
    Date of Patent: March 29, 2016
    Assignee: Intel Corporation
    Inventors: Steven M. Bennett, Andrew V. Anderson, Gilbert Neiger, Richard Uhlig, Scott Dion Rodgers, Rajesh M. Sankaran, Camron Rust, Sebastian Schoenberg