Patents by Inventor Sebastien A. Jean

Sebastien A. Jean has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9977623
    Abstract: A data storage device includes a non-volatile memory and a controller coupled to the non-volatile memory. The controller is configured to receive a first command from an access device, the first command associated with a first logical block address (LBA). The controller is also configured to, after receiving the first command, receive a second command and a third command from the access device. The second command is associated with a second LBA that precedes the first LBA, the third command is associated with a third LBA that succeeds the first LBA. The controller is further configured to determine that the first command, the second command, and the third command correspond to a sequential command stream.
    Type: Grant
    Filed: October 15, 2015
    Date of Patent: May 22, 2018
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Sebastien A. Jean, Noga Deshe, Lilia Brechman, Yan Nosovitsky, Yaron Zamir, Judah Gamliel Hahn
  • Patent number: 9959216
    Abstract: Embodiments for generating and using an enhanced initialization vector are disclosed. In one embodiment, data and a record identifier to which the data is to be written are received. An initialization vector for encrypting the data is then generated. The initialization vector is based on the record identifier and a value that changes every time that the record identifier is to be written to. The value can be generated, for example, by a counter that increments every time the record identifier is to be written to or by a random number generator that generates a random number every time the record identifier is to be written to. In some embodiments, the generated initialization vector is also based on a second value, such as, for example, a value that is shared by other storage modules or a value that is unique to the storage module.
    Type: Grant
    Filed: September 10, 2013
    Date of Patent: May 1, 2018
    Assignee: SanDisk Technologies LLC
    Inventor: Sebastien A. Jean
  • Publication number: 20170109096
    Abstract: A data storage device includes a non-volatile memory and a controller coupled to the non-volatile memory. The controller is configured to receive a first command from an access device, the first command associated with a first logical block address (LBA). The controller is also configured to, after receiving the first command, receive a second command and a third command from the access device. The second command is associated with a second LBA that precedes the first LBA, the third command is associated with a third LBA that succeeds the first LBA. The controller is further configured to determine that the first command, the second command, and the third command correspond to a sequential command stream.
    Type: Application
    Filed: October 15, 2015
    Publication date: April 20, 2017
    Inventors: SEBASTIEN A. JEAN, NOGA DESHE, LILIA BRECHMAN, YAN NOSOVITSKY, YARON ZAMIR, JUDAH GAMLIEL HAHN
  • Patent number: 9542287
    Abstract: Embodiments of the solid-state storage system provided herein are configured to perform improved mechanisms for testing of error recovery of solid state storage devices. In some embodiments, the system is configured to introduce or inject errors into data storage commands or operations performed in the non-volatile memory. Injected errors include corruption of data stored in the non-volatile memory, deliberate failure to execute storage operations, and errors injected into communication protocols used between various elements of the device. In some embodiments, injected errors can include direct errors that trigger an immediate execution of error recovery mechanisms and delayed errors that trigger execution of error recovery mechanisms at a later time. Error recovery mechanisms can be tested in an efficient, reliable, and deterministic manner to help ensure effective operation of storage devices. The integrity of non-volatile memory can also be tested.
    Type: Grant
    Filed: February 20, 2014
    Date of Patent: January 10, 2017
    Assignee: Western Digital Technologies, Inc.
    Inventor: Sebastien A. Jean
  • Patent number: 9195530
    Abstract: A controller-bridge architecture in which a bridge device coupled with the non-volatile memory (NVM) handles inline read-modify-write function under instructions from a controller device is disclosed. In some embodiments, instead of transferring an entire range of data (e.g., a whole NVM page) across a bus between the bridge and the controller twice (once before and once after modification), only the modification data is sent by the controller to the bridge across the bus. The bridge in some embodiments also handles error correction and/or RAID parity striping in the read-modify-write process.
    Type: Grant
    Filed: September 6, 2011
    Date of Patent: November 24, 2015
    Assignee: Western Digital Technologies, Inc.
    Inventor: Sebastien A. Jean
  • Patent number: 9058261
    Abstract: Embodiments of the invention are directed to providing detailed error reporting of data operations performed on a NVM storage device. In one embodiment, a controller interfaces with a NVM storage device including NVM storage coupled with a bridge. In one embodiment, the controller is provided physical, page-level access to the NVM via the bridge, and the bridge provides detailed error reporting of the data operations that the bridge performs on the NVM on behalf of the controller. For example, the bridge may provide page level reporting indicating which page(s) failed during a read operation. Detailed error reporting allows the controller to better understand the failures that occurred in a data access operation in the NVM. It also enables the controller to manage the flash media at the physical page/block level. In one embodiment, detailed error reporting also enables the return of discontinuous ranges of data with the error portions removed.
    Type: Grant
    Filed: February 20, 2014
    Date of Patent: June 16, 2015
    Assignee: Western Digital Technologies, Inc.
    Inventors: Sebastien A. Jean, Robert L. Horn
  • Patent number: 9053008
    Abstract: Disclosed herein is a controller architecture that pairs a controller with a NVM (non-volatile memory) storage system over a high-level, high speed interface such as PCIe. In one embodiment, the NVM storage system includes a bridge that communicates with the controller via the high-level interface, and controls the NVM via an interface. The controller is provided a rich set of physical level of controls over individual elements of the NVM. In one embodiment, the controller includes a volatile memory (e.g., DRAM) that stores parameters related to the operation of the NVM as provided by the bridge. The parameters may be related to optimizing use of the NVM and are automatically appended by the controller to appropriate data storage commands to the bridge. The parameters may be stored in a table format in which each entry is indexed by a physical address of the NVM.
    Type: Grant
    Filed: March 26, 2012
    Date of Patent: June 9, 2015
    Assignee: Western Digital Technologies, Inc.
    Inventors: Robert L. Horn, Sebastien A. Jean
  • Patent number: 9021168
    Abstract: Disclosed herein is a controller architecture that pairs a controller with a NVM (non-volatile memory) storage system over a high-level, high speed interface such as PCIe. In one embodiment, the NVM storage system includes a bridge that communicates with the controller via the high-level interface, and controls the NVM via an interface (e.g., ONFI). The controller is provided a rich set of physical level of controls over individual elements of the NVM. In one embodiment, the controller is implemented in a higher powered processor that supports advanced functions such as mapping, garbage collection, wear leveling, etc. In one embodiment, the bridge is implemented in a lower powered processor and performs basic signal processing, channel management, basic error correction functions, etc. This labor division provides the controller physical control of the NVM over a fast, high-level interface, resulting in the controller managing the NVM at both the page and block level.
    Type: Grant
    Filed: February 20, 2014
    Date of Patent: April 28, 2015
    Assignee: Western Digital Technologies, Inc.
    Inventors: Robert L. Horn, Sebastien A. Jean
  • Publication number: 20150074426
    Abstract: Embodiments for generating and using an enhanced initialization vector are disclosed. In one embodiment, data and a record identifier to which the data is to be written are received. An initialization vector for encrypting the data is then generated. The initialization vector is based on the record identifier and a value that changes every time that the record identifier is to be written to. The value can be generated, for example, by a counter that increments every time the record identifier is to be written to or by a random number generator that generates a random number every time the record identifier is to be written to. In some embodiments, the generated initialization vector is also based on a second value, such as, for example, a value that is shared by other storage modules or a value that is unique to the storage module.
    Type: Application
    Filed: September 10, 2013
    Publication date: March 12, 2015
    Inventor: Sebastien A. Jean
  • Patent number: 8954655
    Abstract: Disclosed herein is an architecture that pairs a controller with a NVM (non-volatile memory) storage system. The NVM storage system includes a bridge device that communicates with the controller. In one embodiment, the bridge device allows for certain data locations (blocks, pages or units at any other granularity) in the flash dies to be (1) placed into a reserved mode where data access is prevented (2) assigned into an SLC (Single-Level Cell) mode or an MLC (Multi-Level Cell) mode in response to controller command, (3) made available for data access after the assignment of mode. This flexibility enables the controller to increase SLC mode or MLC mode data locations based on run-time conditions. In one embodiment, the assignment of the reserved data locations is performed in a way to ensure that warranty conditions imposed by the memory vendors are observed.
    Type: Grant
    Filed: January 14, 2013
    Date of Patent: February 10, 2015
    Assignee: Western Digital Technologies, Inc.
    Inventors: Sebastien A. Jean, Robert L. Horn
  • Patent number: 8713357
    Abstract: Embodiments of the invention are directed to providing detailed error reporting of data operations performed on a NVM storage device. In one embodiment, a controller interfaces with a NVM storage device including NVM storage coupled with a bridge. In one embodiment, the controller is provided physical, page-level access to the NVM via the bridge, and the bridge provides detailed error reporting of the data operations that the bridge performs on the NVM on behalf of the controller. For example, the bridge may provide page level reporting indicating which page(s) failed during a read operation. Detailed error reporting allows the controller to better understand the failures that occurred in a data access operation in the NVM. It also enables the controller to manage the flash media at the physical page/block level. In one embodiment, detailed error reporting also enables the return of discontinuous ranges of data with the error portions removed.
    Type: Grant
    Filed: September 6, 2011
    Date of Patent: April 29, 2014
    Assignee: Western Digital Technologies, Inc.
    Inventors: Sebastien A. Jean, Robert L. Horn
  • Patent number: 8707104
    Abstract: Embodiments of the solid-state storage system provided herein are configured to perform improved mechanisms for testing of error recovery of solid state storage devices. In some embodiments, the system is configured to introduce or inject errors into data storage commands or operations performed in the non-volatile memory. Injected errors include corruption of data stored in the non-volatile memory, deliberate failure to execute storage operations, and errors injected into communication protocols used between various elements of the device. In some embodiments, injected errors can include direct errors that trigger an immediate execution of error recovery mechanisms and delayed errors that trigger execution of error recovery mechanisms at a later time. Error recovery mechanisms can be tested in an efficient, reliable, and deterministic manner to help ensure effective operation of storage devices. The integrity of non-volatile memory can also be tested.
    Type: Grant
    Filed: November 15, 2011
    Date of Patent: April 22, 2014
    Assignee: Western Digital Technologies, Inc.
    Inventor: Sebastien A. Jean
  • Patent number: 8700834
    Abstract: Disclosed herein is a controller architecture that pairs a controller with a NVM (non-volatile memory) storage system over a high-level, high speed interface such as PCIe. In one embodiment, the NVM storage system includes a bridge that communicates with the controller via the high-level interface, and controls the NVM via an interface (e.g., ONFI). The controller is provided a rich set of physical level of controls over individual elements of the NVM. In one embodiment, the controller is implemented in a higher powered processor that supports advanced functions such as mapping, garbage collection, wear leveling, etc. In one embodiment, the bridge is implemented in a lower powered processor and performs basic signal processing, channel management, basic error correction functions, etc. This labor division provides the controller physical control of the NVM over a fast, high-level interface, resulting in the controller managing the NVM at both the page and block level.
    Type: Grant
    Filed: September 6, 2011
    Date of Patent: April 15, 2014
    Assignee: Western Digital Technologies, Inc.
    Inventors: Robert L. Horn, Sebastien A. Jean
  • Publication number: 20130060981
    Abstract: Disclosed herein is a controller architecture that pairs a controller with a NVM (non-volatile memory) storage system over a high-level, high speed interface such as PCIe. In one embodiment, the NVM storage system includes a bridge that communicates with the controller via the high-level interface, and controls the NVM via an interface (e.g., ONFI). The controller is provided a rich set of physical level of controls over individual elements of the NVM. In one embodiment, the controller is implemented in a higher powered processor that supports advanced functions such as mapping, garbage collection, wear leveling, etc. In one embodiment, the bridge is implemented in a lower powered processor and performs basic signal processing, channel management, basic error correction functions, etc. This labor division provides the controller physical control of the NVM over a fast, high-level interface, resulting in the controller managing the NVM at both the page and block level.
    Type: Application
    Filed: September 6, 2011
    Publication date: March 7, 2013
    Applicant: Western Digital Technologies, Inc.
    Inventors: Robert L. Horn, Sebastien A. Jean
  • Patent number: 8176427
    Abstract: A method for a user to easily securely configure a device is provided. The method includes displaying a user interface including a plurality of symbols available for user selection, accepting user inputs including an indication of any symbols selected by the user, converting the symbols selected by the user into numeric data, and assigning the numeric data to configuration parameters for the device.
    Type: Grant
    Filed: December 21, 2006
    Date of Patent: May 8, 2012
    Assignee: Canon Kabushiki Kaisha
    Inventors: Sebastien A. Jean, Swee Huat Sng
  • Publication number: 20100254398
    Abstract: Mimicking network devices with a computing device having first and second network interface cards, the first network interface card connecting the computing device to an external network and the second network interface card connecting the computing device to a local network, including obtaining an IP address of a device on the local network, determining an IP address for the second network interface card based on the obtained IP address of the device on the local network, and assigning the determined IP address to the second network interface card.
    Type: Application
    Filed: June 21, 2010
    Publication date: October 7, 2010
    Applicant: CANON DEVELOPMENT AMERICAS, INC.
    Inventor: Sebastien A. Jean
  • Patent number: 7756956
    Abstract: Mimicking network devices with a computing device having first and second network interface cards, the first network interface card connecting the computing device to an external network and the second network interface card connecting the computing device to a local network, including obtaining an IP address of a device on the local network, determining an IP address for the second network interface card based on the obtained IP address of the device on the local network, and assigning the determined IP address to the second network interface card.
    Type: Grant
    Filed: November 14, 2002
    Date of Patent: July 13, 2010
    Assignee: Canon Development Americas, Inc.
    Inventor: Sebastien A. Jean
  • Patent number: 7552239
    Abstract: The mimicking of network devices in a computing device having first and second network interface cards, the first network interface card connecting the computing device to an external network and the second network interface card connecting the computing device to a local network. The invention includes receiving an incoming message from a client network device residing on the external network, the incoming message being directed to a legacy network device residing on the local network, and determining if the incoming message requires a function provided by an application module residing in the computing device. In the case that the incoming message requires a function provided by the application module, the incoming message is redirected to the application module which performs the required function in response to the incoming message.
    Type: Grant
    Filed: May 14, 2001
    Date of Patent: June 23, 2009
    Assignee: Canon Information Systems, Inc.
    Inventors: Sebastien A. Jean, Don Francis Purpura, Neil Y. Iwamoto
  • Publication number: 20080154851
    Abstract: Embodiments of the present invention can provide means of publicly sharing large files of personal and limited interest over a network. Pursuant to these embodiments, a file possessed by a peer on a network, is shared with another peer on the network by fragmenting the file into data blocks smaller than the original file and transferring these data blocks to other peers on the network where a recipient peer searches for and downloads them.
    Type: Application
    Filed: December 21, 2006
    Publication date: June 26, 2008
    Applicant: CANON KABUSHIKI KAISHA
    Inventor: Sebastien A. Jean
  • Publication number: 20080155402
    Abstract: A method for a user to easily securely configure a device is provided. The method includes displaying a user interface including a plurality of symbols available for user selection, accepting user inputs including an indication of any symbols selected by the user, converting the symbols selected by the user into numeric data, and assigning the numeric data to configuration parameters for the device.
    Type: Application
    Filed: December 21, 2006
    Publication date: June 26, 2008
    Applicant: CANON KABUSHIKI KAISHA
    Inventors: Sebastien A. Jean, Swee Huat Sng